WS57C45

2-25

FUNCTION DESCRIPTION

The WS57C45 is an electrically programmable read only memory produced with WSI’s patented high-performance

self-aligned split gate CMOS EPROM technology. It is organized as 2048 x 8 bits and is pin-for-pin compatible with

bipolar TTL fuse link PROMs. The WS57C45 includes a D-type 8-bit data register on-chip which reduces the

complexity and cost of microprogrammed pipelined systems where PROM data is held temporarily in a register. The

initialization (INIT).

been programmed, the outputs will be in the OFF or high impedance state. If OE has been programmed, the

outputs will be OFF or high impedance only if the OE input is HIGH. Data is read by applying the address to inputs

register during the address set-up time. The data is transferred to the slave output of the data register at the next

When using the asynchronous enable (OE), the output buffers may be disabled at any time by switching the enable

input to a logic HIGH. They may be re-enabled by switching the enable to a logic LOW.

change following a positive clock edge since the output will not change until the next low to high clock transition.

This enables accessing the next data location while previously addressed data is present on the outputs.

To avoid race conditions and simplify system timing, the 8-bit edge triggered data register clock is derived directly

from the system clock.

The WS57C45 has an asynchronous initialize input (INIT). This function can be used during power-up and time-out

periods to implement functions such as a start address or initialized bus control word. The INIT input enables the

contents of a 2049th 8-bit word to be loaded directly into the output data register. The INIT input can be used to

load any 8-bit data pattern into the register since each bit is programmable by the user. When unprogrammed,

activating INIT will result in clearing the register (outputs LOW). When all bits are programmed, actrivating INIT

results in PRESETting the register (outputs HIGH).

When activated LOW, the INIT input results in an immediate load of the 2049th word into both the master and slave

sections of the output register. This is independent of any other input including the clock (CP) input. The initialize

data will be present at the outputs after the asynchronous enable (OE) is taken to a LOW state.

Programming Information

impedance state. Refer to Figure 5. As shown in Figure 5, address, program and verify one byte of data. Repeat

this sequence for each location to be programmed.

When intelligent programming is used, the program pulse width is 1 ms in length. Each address location is

programmed and verified until it verifies correctly up to and including 5 times. After the location verifies, an

additional programming pulse should be applied that is X1 times in duration of the sum of the previous programming

pulses before proceeding on to the next address and repeating the process.

Initialization Byte Programming

The WS57C45 has a 2049th byte of data that can be used to initialize the value of the data register. This byte

contains the value “0” when it is shipped from the factory. The user must program the 2049th byte with a value other

than “0” for data register initialization if that value is not desired. Except for the following details, the user may

program the 2049th byte in the same manner as the other 2048 bytes. First, since all 2048 addresses are used up,

accomplished operationally by performing an initialize function.