MODE

PIN FUNCTION

READ OR OUTPUT DISABLE

CP/PGM

OUTPUTS

Read (Note 6)

X

X

X

Data Out

Output Disable

X

X

X

High Z

Program (Notes 5 & 7)

X

X

Data In

Program Verify (Notes 5 & 7)

X

X

Data Out

Program Inhibit (Notes 5 & 7)

X

X

High Z

Intelligent Program (Notes 5 & 7)

X

X

Data In

Program Synch Enable (Note 7)

High Z

Program Initial Byte (Note 7)

Data In

Initial Byte Read

X

X

X

Data Out

WS57C45

2-26

6. During read operation, the output latches are loaded on a “0” to “1” transition of CP.

Synchronous Enable Programming

The WS57C45 contains both a synchronous and asynchronous enable feature. The part is delivered configured in

the asynchronous mode and only requires alteration if the synchronous mode is required. This is accomplished by

programming an on-chip EPROM cell. Similar to the Initial Byte, this function is enabled and addressed by using a

procedure addresses the EPROM cell that programs the synchronous enable feature. The EPROM cell is

programmed with a 10 ms program pulse on CP/PGM. It does not require any data since there is no selection as to

how synchronous enable may be programmed, only if it is to be programmed.

Synchronous Enable Verification

impedance state.

Blank Check

Upon delivery from WaferScale Integration, Inc. or after each erasure (see Erasure section), the WS57C45 has all

2048 bytes in the ‘0’ state. “1’s” are loaded into the WS57C45 through the procedure of programming.