Preliminary Data Sheet #: TM012

Page 4 of 16

Rev: P06

Date: 05/20/ 02

Pin Description

Table 5

Pin #

Connection

Description

1

Status 0

Mode indicator.

2

Status 1

Mode indicator.

3

LOR

Loss of Reference indicator. 1 = active reference has been lost.

4

PBO

Phase build out indicator. 1 = module is in a phase build out condition.

5

GND

Ground

6

8 kHz Output

Derived from Sync_Out.

7

Reset

Master reset for the module. A low pulse will reset the module. A logic low for a minimum of

1

µs is recommended to ensure a complete reset. This pin is pulled high

internally.

8

Tri-State

Tri-State control for all outputs. 1 = Hi-Z condition, 0 = Normal operation. Pin is pulled low

internally.

9

Hold Over Good

Indicates that the module has acquired enough data to provide an average Hold Over value.

10

Mode Alarm

Alarm indicator output. 1 = Alarm condition, 0 = Normal operation.

11

CNTL A

Mode control input. Pin is pulled low internally.

12

CNTL B

Mode control input. Pin is pulled low internally.

13

RFL

Reference frequency limit alarm for the phase locked loop. 1= Unit is ±15 ppm from Free Run

freq.

14

GND

Ground

15

Sync_Out

System clock output

16

Future Use

Reserved for future use. Do not assert this pin

17

GND

Ground

18

Clock_Out

An independent, Stratum 3 clock output with the required ±4.6 ppm accuracy. May be used as

general purpose clock

19

Future Use

Reserved for future use. Do not assert this pin

20

GND

Ground

21

External Reference 2

External reference #2 input

22

GND

Ground

23

External Reference 1

External reference #1 input

24

+5 V

DC

+5 Volt DC supply

Status 1

Status 0

Mode

0

0

Free Run

0

1

Reference 1

1

0

Reference 2

1

1

Hold Over

Status Outputs

Table 7

CNTL B

CTNL A

Mode Selected

0

0

Free Run

0

1

Reference 1

1

0

Reference 2

1

1

Hold Over

Control Inputs

Table 6