CoreAHB

2

v2.1

Arbitration Scheme

While three masters may be connected to CoreAHB, only

one master can have control of the bus at any one time.

An arbitration mechanism is included in CoreAHB to

control access to the bus by the masters.

In addition to the 3 master connections previously

mentioned, there is also a dummy master contained

within CoreAHB. The dummy master never performs real

transfers, but only issues IDLE transfers if granted. There

is a request input (HBUSREQM0) for the dummy master

that can be connected to a “pause” signal to request

that no other masters are granted control of the bus.

CoreAHB contains a fixed, priority-based, arbitration

scheme that supports three AHB bus masters as well as

the dummy master. The priority allocation is as follows:

•

Master 3 has the highest priority

•

Master 0 (dummy master) has the second highest

priority

•

Master 2 has the middle priority

•

Master 1 has the lowest priority and is the default

bus master. The main subsystem processor (such as

CoreMP7) is normally connected to this master

connection.

Dummy Master

The master 0 slot is reserved for the dummy bus master.

The dummy master does not perform real transfers. It is

granted under the following conditions:

•

When the previously granted master is performing

a locked transfer that has received a SPLIT

response

•

When the default master receives a SPLIT response

and no other master is requesting the bus

•

When all masters have received SPLIT responses

Remapping

CoreAHB has an input named “Remap,” which when

asserted (high) causes slave slots 0 and 1 to be swapped

from the masters’ point of view. Typically, memory

resources such as Flash and RAM will be connected to

slots 0 and 1. The Remap input provides a means of

altering the memory map. For example, it may be

necessary to boot from a nonvolatile memory at power-

up and then subsequently to boot from RAM.

The Remap input can be driven by CoreRemap or by an

external

source.

When

generating

a

subsystem

containing CoreAHB in CoreConsole, the Remap input

will automatically be tied low (inactive) if no connection

is made to it.

Connecting CoreAHB in CoreConsole

Table 1 lists the connections present on CoreAHB and describes how to connect these in CoreConsole.

Table 1 • CoreAHB Bus Connections

Connection

CoreConsole

Label

Description

HCLK

HCLK

AHB system clock input

Connect this to the HCLK output of the bus master.

HRESETn

HRESETn

Active low AHB system reset

Connect this to the HRESETn output of the bus master.

Remap

Remap

This input can be used to modify the memory map. When high, mirrored slave slots

0 and 1 are swapped. This is intended to provide a means of altering the memory

map after boot-up.

This input is tied low if no connection is made to it.

AHB master 0 request

HBUSREQM0

Request input for master 0 (dummy master). This input may be driven by a “pause”

signal to request that no other masters are granted.

This input will be tied low (inactive) if no connection is made to it.

AHB master 0 lock

HLOCKM0

Lock input for master 0 (dummy master).

This input will be tied low (inactive) if no connection is made to it.

AHB master 0 grant

HGRANTM0

Grant indication output for master 0 (dummy master). When high, the dummy

master is driving (IDLE) transfers on the AHB bus.