CoreAHB

4

v2.1

Table 2 • CoreAHB Port List

Signal

Direction Description

Common AHB System Signals

HCLK

Input

Bus clock. This clock times all bus transfers. All signal timings are related to the rising edge of HCLK.

HRESETn

Input

Reset. The bus reset signal is active low and is used to reset the system and the bus. This is the only

active low AHB signal.

Remap Signal

Remap

Input

Provides a means of altering the memory map. Slave slots 0 and 1 are swapped when this input is

high.

Mirrored AHB Master 0 (dummy master) Interface

HBUSREQM0

Input

Request input for master 0 (dummy master). This input may be driven by a “pause” signal to request

that no other masters are granted.

This input will be tied low (inactive) if no connection is made to it.

HLOCKM0

Input

Lock input for master 0 (dummy master).

This input will be tied low (inactive) if no connection is made to it.

HGRANTM0

Output

Grant indication output for master 0 (dummy master). When high, the dummy master is driving (IDLE)

transfers on the AHB bus.

Common AHB Mirrored Master Signals

HRDATA [31:0]

Output

32-bit data to masters

HREADY

Output

Transfer done. When high, the HREADY signal indicates that a transfer has finished on the bus. This

signal can be driven low to extend a transfer.

HRESP[1:0]

Input

Transfer response. This indicates an Okay Error Retry, or Split response.

Master-Specific Mirrored AHB Master Signals

HADDRMx[31:0]

Input

32-bit master address bus (x = 1 to 3)

HTRANSMx [1:0]

Input

Transfer type (x = 1 to 3). Indicates the type of the current transfer:

00 – Idle

01 – Busy

10 – Non-Sequential

11 – Sequential

HWRITEMx

Input

Transfer direction (x = 1 to 3). When high, this signal indicates a write transfer; and when low, a read

transfer.

HSIZEMx [2:0]

Input

Transfer size. This indicates the size of the transfer, which can be byte (8-bit), halfword (16-bit), or

word (32-bit).

HBURSTMx [2:0]

Input

Burst type (x = 1 to 3). This indicates if the transfer forms part of a burst.

HPROTMx [3:0]

Input

Protection control (x = 1 to 3). These signals indicate if the transfer is an opcode fetch or data access,

and if the transfer is a Supervisor mode access or User mode access.

HWDATAMx

[31:0]

Input

32-bit data from master (x = 1 to 3)