CoreAI

v2.0

3

Functional Block Descriptions

CoreAI, shown in Figure 1 on page 2, consists of the

microprocessor interface logic, ACM interface logic, and

ADC interface logic blocks. The microprocessor interface

logic implements APB slave logic and generates a

maskable interrupt. The ACM interface block writes

configuration data into the AB macro to control Analog

Quad and RTC settings. The ADC interface block sends

control data to and receives status information from the

ADC.

CoreAI Device Requirements

CoreAI has been implemented in the Actel Fusion device family. A summary of the data for CoreAI is listed in Table 1

and Table 2.

CoreAI Verification

The comprehensive simulation testbench verifies correct operation of the CoreAI macro.

The testbench applies several tests to the CoreAI macro, including the following:

•

Voltage monitor, current monitor, and temperature monitor tests

•RTC tests

•

Gate-driver control tests

Using the supplied testbench as a guide, the user can alter the verification of the core by adding custom tests or

removing existing tests.

Table 1 • CoreAI Device Utilization and Performance (minimum configuration)

Family

Cells or Tiles

Utilization

Performance

Sequential

Combinatorial

Total

Device

Total

Fusion

45

105

150

AFS090

7%

150 MHz

Note: Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics that differ from the

default values were set as follows: FIXED_VAREFSEL = 1, FIXED_VAREFSEL_VAL = 0, FIXED_MODE = 1, FIXED_MODE_VAL = 0,

FIXED_TVC = 1, FIXED_TVC_VAL = 0, FIXED_STC = 1, FIXED_STC_VAL = 0, CFG_ACx = 512, CFG_ATx = 512, DISABLE_TMSTBINT = 1,

CFG_GDx = 768, ACTLOW_INTERRUPT = 0, DISABLE_INTERRUPT = 1, APB_16BIT_DATA = 1.

Table 2 • CoreAI Device Utilization and Performance (maximum configuration)

Family

Cells or Tiles

Utilization

Performance

Sequential

Combinatorial

Total

FIFO

Device

Total

Fusion

130

330

460

1

AFS090

20%

133 MHz

Note: Data in this table were achieved using typical synthesis and layout settings. Top-level parameters/generics that differ from the

default

values

were

set

as

follows:

ACM_CLK_DIV = 4,

USE_RTC = 1,

USE_RDFIFO = 1,

USE_RDFIFO_AEVAL = 16,

USE_RDFIFO_AFVAL = 240.