CoreAI

6

v2.0

Parameter/Generic Descriptions

CoreAI has parameters (Verilog) and generics (VHDL), described in Table 4, for configuring the RTL code. All

parameters and generics are integer types.

RTCCLK

Input

RTC Clock input – If the RTC is used (via the USE_RTC parameter/generic), this input must

come from the internal crystal oscillator (XTLOSC) CLKOUT pin; if the RTC is not used, this

pin should be tied low.

RTCXTLMODE1,

RTCXTLMODE0

Output

RTC XTLOSC Mode outputs – If the RTC is used (via the USE_RTC parameter/generic), these

output ports must be connected to the internal crystal oscillator (XTLOSC) RTCMODE[1:0]

pins; if the RTC is not used, these pins should be left unconnected.

RTCXTLSEL

Output

RTC XTLOSC Mode Selection output – If the RTC is used (via the USE_RTC parameter/

generic), this output port must be connected to the internal crystal oscillator (XTLOSC)

MODESEL pin; if the RTC is not used, this pin should be left unconnected.

RTCMATCH

Output

RTC Match output – If the RTC is used (via the USE_RTC parameter/generic), this output port

indicates that a match event has occurred and can be connected to other FPGA logic; if the

RTC is not used, this pin should be left unconnected.

RTCPSMMATCH

Output

RTC Match VRPSM output – If the RTC is used (via the USE_RTC parameter/generic), this

output port can be connected to the VRPSM pin of the internal voltage regulator to control

regulator power-up; if the RTC is not used, this pin should be left unconnected.

Table 4 • CoreAI Parameters/Generics Descriptions

Name

Valid Range

Description

APB_16BIT_DATA

0 or 1

Set this to 1 if the APB reads and writes are using all 16-bits of the

PRDATA[15:0] and PWDATA[15:0] ports, or to 0 if 8-bit APB reads and writes

are done on the PRDATA[15:0] and PWDATA[15:0] ports. If 8-bit APB reads

and writes are used, only the lower eight bits of each port are used, i.e.,

PRDATA[7:0] and PWDATA[7:0]; PWDATA[15:8] should be tied statically high

or low and PRDATA[15:8] should be left unconnected in this case. Note that

for 16-bit reads and writes, the internal address map shown in Table 9 on

page 11 will concatenate adjacent bytes since PADDR[0] will be ignored; in

this case, each byte that is addressed by PADDR[0] = 0 will correspond to the

LSB and each byte that is addressed by PADDR[0] = 1 will correspond to the

MSB of each 16-bit word. The default value of 0 uses 8-bit APB reads and

writes.

ACTLOW_INTERRUPT

0 or 1

Interrupt Active Low: Set this to 1 if the INTERRUPT output polarity is active

low, or to 0 if the INTERRUPT output polarity is active high. The default value

of 0 is active high.

DISABLE_INTERRUPT

0 or 1

Disable Interrupt: Set this to 1 if the INTERRUPT output will not be used, in

which case the INTERRUPT output will be fixed at the inactive polarity chosen

by ACTLOW_INTERRUPT, i.e., INTERRUPT = ACTLOW_INTERRUPT; set this to 0

if the INTERRUPT output is used. The default value of 0 uses the INTERRUPT

output.

Note: *Invalid values are 3, 7, 11, and 15 (refer to the

Fusion datasheet).

Table 3 • CoreAI I/O Signal Descriptions (Continued)

Name

Type

Description

Note: All signals active high (logic 1) unless otherwise noted.