COREAI-M datasheet(22/25 Pages) ACTEL

22 / 25 page

CoreAI

v2.0

ADC Operation

Control of the ADC within the AB macro in CoreAI is

accomplished by APB reads and writes. After a power-up

reset condition, the ADC will come out of its reset state

and commence with its internal calibration sequence.

When this calibration sequence has finished, the ADC

will be ready to use for conversions. Read the INT[1:0]

ADC calibration.

The

user

must

configure

the

analog

quads

appropriately via the ACM interface to match the

required

design-specific

voltage,

current,

and

temperature

ranges

prior

performing

ADC

conversions; failure to do so may result in damage to

the Fusion device. The SmartGen software can be used to

configure the analog quads and RTC.

ADC Control

A typical analog-to-digital conversion is shown starting

in Figure 7 and ending in Figure 8 on page 23. The steps

for performing an ADC conversion are as follows:

1. Read the ADC Status register to ensure that the ADC

is not busy calibrating or performing a conversion.

2. Write the desired ADC settings to ADC Control

(internal

external),

mode

selection

(ADC

resolution), and clock divider settings.

3. Write the desired ADC settings to ADC Control

channel number to sample (1 of 32).

4. Set the Start Conversion bit to begin the

conversion process.

5. If a current or temperature monitor operation is

used on a corresponding AC or AT input pin, a write

must be done to set the corresponding current or

temperature monitor strobe high in ADC Control

Refer to the Fusion datasheet for details on

external component connection requirements for

current and temperature monitoring.

6. Keep reading the high-order ADC Status register

until the ADC is not busy performing a conversion.

7. If a current or temperature monitor operation has

completed using a corresponding AC or AT input

pin, a write must be done to set the corresponding

current or temperature monitor strobe low in ADC

Control register 3 or ADC Control register 4,

respectively.

8. Read the low-order ADC Status register to obtain

the lower 8 bits of the resulting ADC conversion

data (the upper 4 bits of conversion data have

already been read from the high-order ADC Status

Note: 8-bit APB reads and writes are shown.

Figure 7 • ADC Start of Conversion

PCLK

PADDR[4:0]

PWRITE

PSEL

PENABLE

PWDATA[7:0]

PRDATA[7:0]

ADCStat(hi)

ADCCtrl1(lo) ADCCtrl1(hi) ADCCtrl2(lo) ADCCtrl2(hi)

ADCStat(hi)

ADC Conversion Starts

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