LTC1402IGN datasheet(12/24 Pages) LINER

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LTC1402

APPLICATIONS INFORMATION

ADC can then be adjusted to match the peak input signal,

maximizing the signal-to-noise ratio. The filtering of the

internal LTC1402 reference amplifier will limit the band-

width and settling time of this circuit. A settling time of

5ms should be allowed after a reference adjustment.

DIFFERENTIAL INPUTS

The LTC1402 has a unique differential sample-and-hold

circuit that allows inputs from –2.5V to 5V. The ADC will

always convert the difference of AIN+ – AIN– independent

of the common mode voltage. The common mode rejec-

tion holds up at extremely high frequencies, see Figure 7.

The only requirement is that both inputs not exceed

– 2.5V or 5V. Integral nonlinearity errors (INL) and differ-

ential nonlinearity errors (DNL) are independent of the

common mode voltage. However, the bipolar zero error

(BZE) will vary. The change in BZE is typically less than

0.1% of the common mode voltage. Figure 5b shows the

use of bipolar mode with single 5V supply.

Figure 5a. Using the LT1019-2.5 as an External Reference

LTC1402

LT1019-2.5

AIN

ANALOG INPUT

AIN

–

VREF

VOUT

VIN

AGND2

GAIN

1402 F04a

µF

LTC1402

LT1019-2.5

AIN

VIN

2.5V

±2.048V

AIN

–

VREF

BIP

VIN

AGND2

VSS

GAIN

1402 F04a

µF

2.5V

Figure 5b. Bipolar Mode with Single Supply

Figure 6. Driving VREF with a 12 Bit, VOUT DAC

LTC1402

AIN

ANALOG INPUT

AIN

–

VREF

AGND2

GAIN

1402 F06

µF

LTC1451

INTERNAL REFERENCE

The LTC1402 has an on-chip, temperature compensated,

curvature corrected, bandgap reference that is factory

trimmed to 2.048V. It is connected internally to a reference

amplifier, see Figure 4. The reference amplifier amplifies

the voltage at the VREF pin by 2 to create the required

internal reference voltage of 4.096V. This provides buffer-

ing for the high speed capacitive DAC. The reference

amplifier output VREF, (Pin 5) must be bypassed with a

capacitor to ground. The reference amplifier is stable with

capacitors of 1

µF or greater. For the best noise perfor-

mance, a 10

µF ceramic or a 10µF tantalum in parallel with

a 0.1

µF ceramic is recommended.

The VREF pin can be driven with an external reference as

shown in Figure 5a. The GAIN pin (Pin 7) is tied to the

positive supply to disable the internal reference buffer.

A DAC may also be used to drive VREF as shown in

Figure 6. This is useful in applications where the peak

input signal amplitude may vary. The input span of the

Figure 4. LTC1402 Reference Circuit

64k

REFERENCE

AMP

µF

GAIN

VREF

BANGAP

REFERENCE

AGND2

4.096V

LTC1402

–

2.048V

1402 F04

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