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LTC1402

Figure 14. DSP Serial Interface to TMS320C54x

HARDWARE INTERFACE TO TMS320C54x

The LTC1402 is a serial output ADC whose interface has

been designed for high speed buffered serial ports in fast

digital signal processors (DSPs). Figure 14 shows an

example of this interface using a TMS320C54X.

The buffered serial port in the TMS320C54x has direct

access to a 2kB segment of memory. The ADC’s serial data

can be collected in two alternating 1kB segments, in real

time, at the full 2.2Msps conversion rate of the LTC1402.

The DSP assembly code sets frame sync mode at the BFSR

pin to accept an external positive going pulse, and the

serial clock at the BCLKR pin to accept an external positive

edge clock. Buffers near the LTC1402 may be added to

drive long tracks to the DSP to prevent corruption of the

signal to LTC1402. This configuration is adequate to

traverse a typical system board, but source resistors at the

buffer outputs, and termination resistors at the DSP may

be needed to match the characteristic impedance of very

long transmission lines. If you need to terminate the DOUT

transmission line, buffer it first with one or two 74ACxx

gates. The TTL threshold inputs of the DSP port respond

properly to the 2.5V swing of the terminated transmission

lines. The OVDD supply output driver supply voltage can be

driven directly from the DSP.

APPLICATIONS INFORMATION

1402 F14

3-WIRE SERIAL

INTERFACELINK

OVDD

CONV

SCK

LTC1402

DOUT

VCC

BFSR

BCLKR

TMS320C54x

BDR

OGND

CONV

CLK

REF

B11

B10

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