LTC6943

6

6943f

Figure 2. CMRR vs Sampling Frequency

Figure 3

APPLICATIO S I FOR ATIO

100

20

100

120

140

1k

10k

100k

6943 • AI02

80

60

40

6943 • AI03

1/8 LTC6943

5

SAMPLE

HOLD TO PIN 14

0V

1000pF

5V

–5V

–

+

1

1/2 LTC1013

respect to an input CM voltage variation. During the

sampling and holding mode, charges are being trans-

ferred and minute voltage transients will appear across the

enough to allow fast settling, as the sampling frequency

increases, the rate of charge transfer increases and the

average voltage measured with a DVM across it will

increase proportionally; this causes the CMRR of the

sampled data system, as seen by a “continuous” instru-

ment (DVM), to decrease (Figure 2).

Switch Charge Injection

Figure 3 shows one out of the eight switches of the

LTC6943, configured as a basic sample-and-hold circuit.

When the switch opens, a ‘‘hold step’’ is observed and its

magnitude depends on the value of the input voltage.

Figure 4 shows charge injected into the hold capacitor. For

instance, a 2pCb of charge injected into a 0.01µF capacitor

causes a 200µV hold step. As shown in Figure 4, there is

a predictable and repeatable charge injection cancellation

when the input voltage is close to half the supply voltage

of the LTC6943. This is a unique feature of this product,

containing charge-balanced switches fabricated with a

self-aligning gate CMOS process. Any switch of the

LTC6943, when powered with symmetrical dual supplies,

will sample-and-hold small signals around ground with-

out any significant error.

Shielding the Sampling Capacitor for Very High CMRR

to ground affect the CMRR of the LTC6943 (Figure 1).

The common mode error due to the internal junction

the top plate of the sampling capacitor. A shield placed

helps to boost the CMRR to 120dB (Figure 5).

pins and ground indirectly degrades CMRR; this becomes

visible especially when the LTC6943 is used with clock

frequencies above 2kHz. Because of this, if a shield is

used, the parasitic capacitance between the shield and

circuit ground should be minimized.

It is recommended that the outer plate of the sampling

connected from Pin 14 to Pin 15, to modify the internal

oscillator frequency. If Pin 16 is floating, the internal 24pF

capacitor, plus any external interpin capacitance, set the

oscillator frequency around 190kHz with ±5V supply. The

typical performance characteristics curves provide the

necessary information to set the oscillator frequency for

various power supply ranges. Pin 14 can also be driven

with an external CMOS level clock to override the internal

oscillator.