LTC3545 datasheet(14/20 Pages) LINER

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LTC3545/LTC3545-1

35451fb

1. The quiescent current is due to two components: the

DC bias current as given in the electrical characteristics

and the internal main switch and synchronous switch

gate charge currents. The gate charge current results

from switching the gate capacitance of the internal power

MOSFET switches. Each time the gate is switched from

high to low to high again, a packet of charge, dQ, moves

from PVIN to ground. The resulting dQ/dt is the current out

of PVIN that is typically larger than the DC bias current and

proportional to frequency. Both the DC bias and gate charge

losses are proportional to PVIN and thus their effects will

be more pronounced at higher supply voltages.

2. I2R losses are calculated from the resistances of the

internal switches, RSW, and external inductor RL. In con-

tinuous mode, the average output current ﬂowing through

inductor L is “chopped” between the main switch and the

synchronous switch. Thus, the series resistance looking

into the SW pin is a function of both top and bottom

MOSFET RDS(ON) and the duty cycle (DC) as follows:

RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can

be obtained from the Typical Performance Characteristics

curves. Thus, to obtain I2R losses, simply add RSW to

RL and multiply the result by the square of the average

output current.

Other losses when in switching operation, including CIN

and COUT ESR dissipative losses and inductor core losses,

generally account for less than 2% total additional loss.

Thermal Considerations

The LTC3545/LTC3545-1 requires the package backplane

metal to be well soldered to the PC board. This gives the

QFN package exceptional thermal properties, making

it difﬁcult in normal operation to exceed the maximum

junction temperature of the part. In most applications the

LTC3545/LTC3545-1 do not dissipate much heat due to

their high efﬁciency. In applications where the LTC3545/

LTC3545-1 are running at high ambient temperature

with low supply voltage and high duty cycles, such as in

dropout, the heat dissipated may exceed the maximum

junction temperature of the part if it is not well thermally

grounded. If the junction temperature reaches approxi-

mately 150°C, the power switches will be turned off and

the SW nodes will become high impedance.

To prevent the LTC3545/LTC3545-1 from exceeding the

maximum junction temperature, the user will need to do

some thermal analysis. The goal of the thermal analysis

is to determine whether the power dissipated exceeds the

maximum junction temperature of the part. The tempera-

ture rise is given by:

TR = PD • θJA

where PD is the power dissipated by the regulator and θJA

is the thermal resistance from the junction of the die to

the ambient temperature.

The junction temperature, TJ, is given by:

TJ = TA + TR

where TA is the ambient temperature.

As an example, consider one channel of the LTC3545/

LTC3545-1 in dropout at an input voltage of 2.5V, a load

current of 800mA, and an ambient temperature of 85°C.

From the typical performance graph of switch resistance,

the RDS(ON) of the P-channel switch at 85°C can be es-

timated as 0.42

Ω. Therefore, power dissipated by the

channel is:

PD = ILOAD2 • RDS(ON) = 0.27W

The

θJA for the 3mm × 3mm QFN package is 68°C/W. The

temperature rise due to this power dissipation is:

TR = θJA • PD = 18°C

And a junction temperature of:

TJ = 85°C + 18°C = 103°C

which is below the maximum junction temperature of

125°C. This would not be the case if all three channels

were operating at 800mA in dropout. Then TR = 55°C,

limiting the allowed ambient temperature in this scenario

to less than 70°C.

APPLICATIONS INFORMATION

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