74AC11245

OCTAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCAS010B – JULY 1987 – REVISED APRIL 1996

1

POST OFFICE BOX 655303

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

mm Process

125

°C

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, and Standard Plastic 300-mil

DIPs (NT)

description

This octal bus transceiver is designed for asynchronous two-way communication between data buses. The

control-function implementation minimizes external timing requirements.

The device allows noninverted data transmission from the A bus to the B bus or from the B bus to the A bus,

depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to

disable the device so that the buses are effectively isolated.

The 74AC11245 is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

OUTPUT

ENABLE

OE

DIRECTION

CONTROL

DIR

OPERATION

L

L

B data to A bus

L

H

A data to B bus

H

X

Isolation

Copyright

© 1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

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A1

A2

A3

A4

GND

GND

GND

GND

A5

A6

A7

A8

DIR

B1

B2

B3

B4

B5

B6

B7

B8

OE

DB, DW, NT, OR PW PACKAGE

(TOP VIEW)