DAC7802LP datasheet(4/17 Pages) TI

4 / 17 page

DAC7800, 7801, 7802

SBAS005A

www.ti.com

DATA

CLK

UPD A

UPD B

CLR

NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns.

(2) Timing measurement reference level is V + V

PARAMETER

MINIMUM

t1 — Data Setup Time

15ns

t2 — Data Hold Time

15ns

t3 — Chip Select to CLK,

15ns

Update, Data Setup Time

t4 — Chip Select to CLK,

40ns

Update, Data Hold Time

t5 — CLK Pulse Width

40ns

t6 — Clear Pulse Width

40ns

t7 — Update Pulse Width

40ns

t8 — CLK Edge to UPD A

15ns

or UPD B

TIMING CHARACTERISTICS

VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.

Data In

Bit 0

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

DAC A

MSB

DAC A

LSB

DAC B

MSB

DAC B

DAC7800 Data Input Sequence

DAC7800 Digital Interface Block Diagram

24-Bit

Shift Register

DAC A Register

UPD A

Data In

CLK

UPD B

LSB

MSB

DAC B Register

LSB

MSB

Bit

CLK

DATA INPUT FORMAT

DAC7800 (Cont.)

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