DAC7800, 7801, 7802

6

SBAS005A

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BLOCK DIAGRAM

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

AGND

I

R

V

CS A

(LSB) DB0

DB1

DB2

DB3

DB4

DB5

DGND

I

R

V

V

CS B

WR

DB11 (MSB)

DB10

DB9

DB8

DB7

DB6

OUT A

FB A

REF A

FB B

REF B

DD

OUT B

DAC7802

TIMING CHARACTERISTICS

PARAMETER

MINIMUM

20ns

15ns

30ns

0ns

30ns

LOGIC TRUTH TABLE

CSA

CSB

WR

FUNCTION

X

X

1

No Data Transfer

1

1

X

No Data Transfer

0

A Rising Edge on CSA or CSB Loads

Data to the Respective DAC

01

DAC A Register Loaded from Data Bus

10

DAC B Register Loaded from Data Bus

00

DAC A and DAC B Registers Loaded

from Data Bus

X = Don’t care.

means rising edge triggered.

PIN CONFIGURATION

DAC7802

DATA

5V

0V

5V

5V

CSA, CSB

WR

t

2

t

1

t

3

t

4

t

5

NOTES: (1) All input signal rise and fall times are measured from 10%

to 90% of +5V. t

is

V

2

.

CK

DAC B

DAC A

12

12

12

12

12

DGND

18

CS A

5

CS B

20

WR

19

21

V

DD

DAC7802

6

2

I

3

R

OUT A

FB A

23

R

24

I

1

AGND

FB B

OUT B

DAC A Register

CK

DAC B Register

DB11–DB0

4

22

V

V

REF A

REF B

Top View

DIP