PCA8550

NONVOLATILE 5-BIT REGISTER

SCPS050A – MARCH 1999 – REVISED APRIL 1999

1

POST OFFICE BOX 655303

CMOS) Submicron Process

Motherboard

Small-Outline (D), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages

description

nonvolatile register. An additional bit of register output also is provided, which is latched to prevent changes in

the output value during the write cycle. The factory default for the contents of the register is all low. These stored

by the write protect (WP) input. The override (OVERRIDE) input forces all the register outputs to a low.

The PCA8550 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

MUX SELECT

OVERRIDE

MUX OUT

NON-MUXED

OUT

L

L

L

L

L

H

Nonvolatile

register

Nonvolatile

register

H

X

MUX IN

Latched

NON-MUXED

OUT†

† The latched NON-MUXED OUT state is the value present on the

NON-MUXED OUT output at the time the MUX SELECT input

transitions from the low to the high state.

Copyright

© 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

OVERRIDE

MUX IN A

MUX IN B

MUX IN C

MUX IN D

GND

WP

NON-MUXED OUT

MUX SELECT

MUX OUT A

MUX OUT B

MUX OUT C

MUX OUT D

D, DB, OR PW PACKAGE

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