LPC2158 datasheet(25/45 Pages) PHILIPS

25 / 45 page

LPC2157_2158_2

Product data sheet

Rev. 02 — 9 February 2009

25 of 45

NXP Semiconductors

LPC2157/2158

Single-chip 16-bit/32-bit microcontrollers

6.19.4 Brownout detector

The LPC2157/2158 include 2-stage monitoring of the voltage on the VDD pins. If this

voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal can

be enabled for interrupt; if not, software can monitor the signal by reading dedicated

The second stage of low voltage detection asserts reset to inactivate the LPC2157/2158

when the voltage on the VDD pins falls below 2.6 V. This reset prevents alteration of the

ﬂash as operation of the various elements of the chip would otherwise become unreliable

due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point

the POR circuitry maintains the overall reset.

Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event

loop to sense the condition.

6.19.5 Code security

This feature of the LPC2157/2158 allow an application to control whether it can be

debugged or protected from observation.

If after reset on-chip bootloader detects a valid checksum in ﬂash and reads 0x8765 4321

from address 0x1FC in ﬂash, debugging will be disabled and thus the code in ﬂash will be

protected from observation. Once debugging is disabled, it can be enabled only by

performing a full chip erase using the ISP.

6.19.6 External interrupt inputs

The LPC2157/2158 include up to nine edge or level sensitive external interrupt inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The external interrupt inputs can optionally be used

to wake-up the processor from Power-down mode.

Additionally capture input pins can also be used as external interrupts without the option

to wake the device up from Power-down mode.

6.19.7 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

6.19.8 Power control

The LPC2157/2158 supports two reduced power modes: Idle mode and Power-down

mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

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