CDK1301 datasheet(2/12 Pages) CADEKA

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Data Sheet

Pin Configuration

TQFP-44

CDK1301

Pin Assignments

Pin No.

Pin Name

Description

VIN+

Non-inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally

VIN-

Inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally

16-9

DA0–DA7

Data output bank A; 3V/5V LVCMOS compatible

19-26

DB0–DB7

Data output bank B; 3V/5V LVCMOS compatible

DCLKOUT

Non-inverted data output clock; 3v/5v 3V/5V LVCMOS compatible

DCLKOUT

Inverted data output clock; 3V/5V LVCMOS compatible

CLK

Non-inverted clock input pin; 100k pulldown to AGND, internally

CLK

Inverted clock input pin; 17.5k pullup to Vcc and 7.5k pulldown to AGND, internally

RESET

RESET synchronizes the data sampling and data output bank relationship when in dual channel

mode (DMODE1 = 0); 100k pulldown to AGND, internally

RESET

Inverted RESET input pin; 17.5k pullup to Vcc and 7.5 pulldown to AGND, internally

32, 31

DMODE1,2

Internally: 100k pulldown to AGND on DMODE1 50k pullup to Vcc on DMODE2

Data output mode pins: DMODE1 = 0, DMODE2 = 0: parallel dual channel output

DMODE1 = 0, DMODE2 = 1: interleaved dual channel output

DMODE1 = 1, DMODE2 = x: single channel data output on bank a (125 MSPS max)

Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down

mode; 100k pulldown to AGND, internally

VCM

2.5V common mode voltage reference output

35, 36,

42, 43

AVCC

+5V analog supply

7, 17, 30

OVDD

+3V/+5V digital output supply

1, 33, 34,

38, 41, 44

AGND

Analog ground

8, 18, 29

DGND

Digital ground

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