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6

Data Sheet

Specification Definitions

aperture Delay

Aperture delay represents the point in time, relative to

the rising edge of the CLOCK input, that the analog input

is sampled.

aperture Jitter

The variations in aperture delay for successive samples.

Differential Gain (DG)

A signal consisting of a sine wave superimposed on vari-

ous DC levels is applied to the input. Differential gain is

the maximum variation in the sampled sine wave ampli-

tudes at these DC levels.

Differential phase (Dp)

A signal consisting of a sine wave superimposed on vari-

ous DC levels is applied to the input. Differential phase is

the maximum variation in the sampled sine wave phases

at these DC levels.

effective number of Bits (enoB)

SINAD = 6.02N + 1.76, where N is equal to the effective

number of bits.

N = SINAD – 1.76

6.02

input Bandwidth

Small signal (50mV) bandwidth (3dB) of analog input stage.

Differential linearity error (Dle)

Error in the width of each code from its theoretical value.

integral linearity error (ile)

Linearity error refers to the deviation of each individual

code (normalized) from a straight line drawn from –FS

through +FS. The deviation is measured from the edge of

each particular code to the true straight line.

output Delay

Time between the clock’s triggering edge and output data

valid.

overvoltage recovery time

The time required for the ADC to recover to full accuracy

after an analog input signal 125% of full scale is reduced

to 50% of the full-scale value.

signal-to-noise ratio (snr)

The ratio of the fundamental sinusoid power to the total

noise power. Harmonics are excluded.

signal-to-noise and Distortion (sinaD)

The ratio of the fundamental sinusoid power to the total

noise and distortion power.

total Harmonic Distortion (tHD)

The ratio of the total power of the first 9 harmonics to the

power of the measured sinusoidal signal.

spurious free Dynamic range (sfDr)

The ratio of the fundamental sinusoidal amplitude to the

single largest harmonic or spurious signal.

Figure 1. Timing Diagram 1