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CDK1306 数据表(PDF) 4 Page - Cadeka Microcircuits LLC. |
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CDK1306 数据表(HTML) 4 Page - Cadeka Microcircuits LLC. |
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4 / 11 page  ©2008 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Electrical Characteristics (TA = TMin to TMax, AVDD = DVDD = OVDD = +5V, VIN = 0 to 4V, ƒclk = 40 MSPS, VRHS = 4V, VRLS = 0V; unless otherwise noted) symbol parameter conditions Min typ Max units Resolution 10 bits DC Performance DLE Differential Linearity Error(1) -0.5 +0.5 LSB ILE Integral Linearity Error(1) -1.0 +1.0 LSB No Missing Codes Guaranteed Analog Input Input Voltage Range(1) VRLS VRHS V Input Resistance(2) 50 kΩ Input Capacitance 5 pF Input Bandwidth Small Signal 250 MHz Gain Error ±2.0 LSB Offset Error ±2.0 LSB Reference Input Resistance(1) 200 400 600 Ω Bandwidth Small Signal 150 MHz Voltage Range VRLS(2) 0 2.0 V VRHS(2) 3.0 AVDD V VRHS – VRLS 4.0 V Δ (VRHF – VRHS) 90 mV Δ (VRLS – VRLF) 75 mV Reference Settling Time VRHS 15 CLK Cycle VRLS 20 CLK Cycle Conversion Characteristics Maximum Conversion Rate(1) 40 MHz Minimum Conversion Rate(2) 2 MHz Pipeline Delay (Latency)(2) 12 CLK Cycle Aperture Delay Time 4.0 ns Aperture Jitter Time 15 pspp Dynamic Performance ENOB Effective Number of Bits ƒIN = 3.58MHz 9.2 Bits ƒIN = 10.3MHz 8.8 Bits SNR Signal-to-Noise Ratio w/o Harmonics ƒIN = 3.58MHz(1) 56 58 dB ƒIN = 10.3MHz(1) 55 57 dB THD Total Harmonic Distortion ƒIN = 3.58MHz(1), 9 distortion bins from 1024 pt FFT 61 63 dB ƒIN = 10.3MHz(1), 9 distortion bins from 1024 pt FFT 56 58 dB SINAD Signal-to-Noise and Distortion ƒIN = 3.58MHz(1) 54 57 dB ƒIN = 10.3MHz(1) 53 55 dB SFDR Spurious Free Dynamic Range ƒIN = 1MHz 64 dB Differential Phase ±0.3 deg Differential Gain ±0.3 % notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. |
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