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ADVANCE Data Sheet

designed by

Amplify the Human Experience

Mechanical Dimensions

QFN-40 Package

NOTE:

Package dimensions in millimeter unless otherwise noted.

Symbol

Min

Typ

Max

Min

Typ

Max

A

–

–

0.035

–

–

0.9

0.001

0.0004

0.002

0.00

0.01

0.05

–

0.023

0.028

–

0.65

0.7

0.008 REF

0.2 REF

b

0.008

0.010

0.013

0.2

0.25

0.32

D

0.236 BSC

6.00 BSC

0.226 BSC

5.75 BSC

0.156

0.162

0.167

3.95

4.10

4.25

L

0.012

0.016

0.020

0.3

0.4

0.5

e

0.020 BSC

0.50 BSC

1

0°

–

12°

0°

–

12°

F

0.008

–

–

0.2

–

–

G

0.0096

0.0168

0.024

0.24

0.42

0.6

R

0.004

0.008

–

0.1

0.2

–

Inches

Millimeters

Pin 1 ID - Dia. 0.5

(Top Side)

Pin 1 ID - Dia. R

Pin 0 Exposed Pad

F

G

A

A3

A1

A2

1

L

b

e

1.14

0.45

D

D2

D

D2

D1

Reference Voltages

The reference voltages are internally generated and buff-

ered based on a bandgap voltage reference. No external

decoupling is necessary, and the reference voltages are

not available externally. This simplifies usage of the ADC

since two extremely sensitive pins, otherwise needed, are

removed from the interface.

Operational Modes

The operational modes are controlled with the PD_N and

SLP_N pins. If PD_N is set low, all other control pins are

overridden and the chip is set in Power Down mode. In

this mode all circuitry is completely turned off and the in-

ternal clock is disabled. Hence, only leakage current con-

tributes to the Power Down Dissipation. The startup time

from this mode is longer than for Sleep Mode as all refer-

ences need to settle to their final values before normal

operation can resume.

The SLP_N signal can be used to set the full chip in Sleep

Mode. In this mode internal clocking is disabled, but some

low bandwidth circuitry is kept on to allow for a short

startup time. However, Sleep Mode represents a signifi-

cant reduction in supply current, and it can be used to

save power even for short idle periods.

The input clock should be kept running in all idle modes.

However, even lower power dissipation is possible in Power

Down mode if the input clock is stopped. In this case it is

important to start the input clock prior to enabling active mode.