Data Sheet

©2007-2008 CADEKA Microcircuits LLC

www.cadeka.com

13

Application Information

Basic Operation

Figures 1 and 2 illustrate typical circuit configurations for

non-inverting, inverting, and unity gain topologies for dual

supply applications. They show the recommended bypass

capacitor values and overall closed loop gain equations.

+

-

0.1μF

6.8μF

Output

Input

0.1μF

6.8μF

Figure 1. Typical Non-Inverting Gain Circuit

Figure 2. Typical Inverting Gain Circuit

Achieving Low Noise in an Application

Making full use of the low noise of the CLC1001 requires

careful consideration of resistor values. The feedback and

can easily dominate the overall noise if their values are

the noise from the CLC1001. Lower value resistors could

be used at the expense of more distortion. Figure 3 shows

noise also increases.

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

2.75

100

1000

Rf (Ohms)

G = +11

G = +21

G = +41

The noise caused by a resistor is modeled with either a

voltage source in series with the resistance:

4kTR

Or a current source in parallel with it:

i

R

4kT

The noise models must be analyzed in-circuit to deter-

mine the effect on the op amp output noise.

Since noise is statistical in nature rather than a continuous

signal, the set of noise sources in circuit add in an RMS

(root mean square) fashion rather than in a linear fashion.

For uncorrelated noise sources, this means you add the

squares of the noise voltages. A typical non-inverting ap-

plication (see figure 1) results in the following noise at the

output of the op amp:

+

-

0.1μF

6.8μF

Output

For optimum input offset

Input

0.1μF

6.8μF