CLC1001 datasheet(15/17 Pages) CADEKA

15 / 17 page

Data Sheet

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Driving Capacitive Loads

Increased phase delay at the output due to capacitive load-

ing can cause ringing, peaking in the frequency response,

and possible unstable behavior. Use a series resistance,

RS, between the amplifier and the load to help improve

stability and settling performance. Refer to Figure 5.

Input

Output

Figure 5. Addition of RS for Driving

Capacitive Loads

Table 1 provides the recommended RS for various capaci-

tive loads. The recommended RS values result in <=1dB

peaking in the frequency response. The Frequency Re-

sponse vs. CL plots, on page 7, illustrates the response of

the CLC1001.

CL (pF)

RS (Ω)

-3dB BW (MHz)

266

228

192

100

155

470

4.3

Table 1: Recommended RS vs. CL

For a given load capacitance, adjust RS to optimize the

tradeoff between settling time and bandwidth. In general,

reducing RS will increase bandwidth at the expense of ad-

ditional overshoot and ringing.

Overdrive Recovery

An overdrive condition is defined as the point when either

one of the inputs or the output exceed their specified volt-

age range. Overdrive recovery is the time needed for the

amplifier to return to its normal or linear operating point.

The recovery time varies, based on whether the input or

output is overdriven and by how much the range is ex-

ceeded. The CLC1001 will typically recover in less than

25ns from an overdrive condition. Figure 6 shows the

CLC1001 in an overdriven condition.

-6

-4

-2

-3

-2

-1

100

150

200

250

300

350

400

450

Time (us)

Output

Input

G = 10

Figure 6. Overdrive Recovery

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. CaDeKa has evaluation

boards to use as a guide for high frequency layout and as

aid in device testing and characterization. Follow the steps

below as a basis for high frequency layout:

• Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more in-

formation.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

Products

CEB002

CLC1001 in SOT23-5

CEB003

CLC1001 in SOIC-8

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