TLE2071IP datasheet(68/77 Pages) TI

68 / 77 page

TLE207x, TLE207xA, TLE207xY

EXCALIBUR LOW-NOISE HIGH-SPEED

JFET-INPUT OPERATIONAL AMPLIFIERS

SLOS181A – FEBRUARY 1997 – REVISED MARCH 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

input characteristics

The TLE207x, TLE207xA, and TLE207xB are specified with a minimum and a maximum input voltage that if

exceeded at either input could cause the device to malfunction. Because of the extremely high input impedance

and resulting low bias current requirements, the TLE207x, TLE207xA, and TLE207xB are well suited for

low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed

bias current requirements and cause degradation in system performance. It is good practice to include guard

rings around inputs (see Figure 70). These guards should be driven from a low-impedance source at the same

voltage level as the common-mode input.

–

+ R2

Where

Figure 70. Use of Guard Rings

TLE2071 input offset voltage nulling

The TLE2071 series offers external null pins that can be used to further reduce the input offset voltage. The

circuit of Figure 71 can be connected as shown if the feature is desired. When external nulling is not needed,

the null pins may be left unconnected.

–

VCC –

100 k

Ω

5 k

Ω

IN –

IN +

OUT

Figure 71. Input Offset Voltage Nulling

TLE2071IP 数据表(PDF) 68 Page - Texas Instruments