www.ti.com

APPLICATION INFORMATION

GENERAL FUNCTION

2 REF

CODE

0 1000

[V]

PARALLEL INTERFACE

TLV5633C

TLV5633I

SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006

The TLV5633 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel

interface, a speed and power down control logic, a programmable internal reference, a resistor string, and a

rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by:

Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power

on reset initially puts the internal latches to a defined state (all bits zero).

The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written

to one of the DAC holding latches (MSW, LSW) or the control register depends on the address bits A1 and A0.

LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held

low, if a separate update is not necessary. However, to control the DAC using the load feature, there should be

approximately a 5 ns delay after the positive WE edge before driving LDAC low. Two more asynchronous inputs,

SPD and PWR control the settling times and the power-down mode:

SPD:

Speed control

1

→ fast mode

0

→ slow mode

PWR:

Power control

1

→ normal operation

0

→ power down

It is also possible to program the different modes (fast, slow, power down) and the DAC update latch using the

control register. The following tables list the possible combinations of control signals and control bits.

PIN

BIT

MODE

SPD

SPD

0

0

Slow

0

1

Fast

1

0

Fast

1

1

Fast

PIN

BIT

POWER

PWR

PWD

0

0

Down

0

1

Down

1

0

Normal

1

1

Down

PIN

BIT

LATCH

LDAC

RLDAC

0

0

Transparent

0

1

Transparent

1

0

Hold

1

1

Transparent

11

Submit Documentation Feedback