TLV5633CPWR datasheet(12/23 Pages) TI

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DATA FORMAT

LAYOUT CONSIDERATIONS

TLV5633C

TLV5633I

SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006

The TLV5633 writes data either to one of the DAC holding latches or to the control register depending on the

address bits A1 and A0.

ADDRESS BITS

DAC LSW holding

DAC MSW holding

Reserved

Control

The following table lists the meaning of the bits within the control register.

REF1

REF0

RLDAC

PWR

SPD

X(1)

0(1)

(1)

Default values: X = Don't Care

SPD: Speed control bit

→ fast mode

→ slow mode

PWR: Power control bit

→ power down

→ normal operation

RLDAC: Load DAC latch

→ latch transparent 0 → DAC latch controlled by LDAC pin

REF1 and REF0 determine the reference source and the reference voltage.

REFERENCE BITS

REF1

REF0

REFERENCE

External

1.024 V

2.048 V

External

If an external reference voltage is applied to the REF pin, external reference must be selected.

To achieve the best performance, it is recommended to have separate power planes for GND, AVDD, and DVDD.

Figure 13 shows how to lay out the power planes for the TLV5633. As a general rule, digital and analog signals

should be separated as wide as possible. To avoid crosstalk, analog and digital traces must not be routed in

parallel. The two positive power planes (AVDD and DVDD) should be connected together at one point with a

ferrite bead.

A 100-nF ceramic low series inductance capacitor between DVDD and GND and a 1-µF tantalum capacitor

between AVDD and GND placed as close as possible to the supply pins are recommended for optimal

performance.

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