TMS320UC5402 datasheet(21/63 Pages) TI

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TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

DMA in autoinitialization mode

The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can

be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and

DMGCR). Autoinitialization allows:

D Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the

completion of the current block transfer; but with the global reload registers, it can reinitialize these values

for the next block transfer any time after the current block transfer begins.

D Repetitive operation: The CPU does not preload the global reload register with new values for each block

transfer but only loads them on the first block transfer.

DMA transfer counting

The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields

that represent the number of frames and the number of elements per frame to be transferred.

D Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number

of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the last read

transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with

the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default

value) means the block transfer contains a single frame.

D Element count. This 16-bit value defines the number of elements per frame. This counter is decremented

after the read transfer of each element. The maximum number of elements per frame is 65536

(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded

with the DMA global count reload register (DMGCR).

DMA transfers in double-word mode

Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two

consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated

following each transfer. In this mode, each 32-bit word is considered to be one element.

DMA channel index registers

The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode

control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and

DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is

the last in the current frame. The normal adjustment value (element index) is contained in the element index

registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by

the selected DMA frame index register, either DMFRI0 or DMFRI1.

The element index and the frame index affect address adjustment as follows:

D Element index: For all except the last transfer in the frame, the element index determines the amount to be

added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by

the SIND/DIND bits.

D Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as selected

by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.

TMS320UC5402 数据表(PDF) 21 Page - Texas Instruments

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