TMS320VC549 datasheet(39/111 Pages) TI

39 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory-mapped registers

Most ’54x devices have 26 (except ’548 and ’549 have 27) memory-mapped CPU registers, which are mapped

into data memory located at addresses 0h to 1Fh. Each of these devices also has a set of memory-mapped

registers associated with peripherals. Table 7 gives a list of CPU memory-mapped registers (MMR) common

to all ’54x devices. Table 8 shows additional peripheral MMRs associated with the ’541 devices, Table 9 shows

those associated with the ’545/’546 devices, Table 10 shows those associated with the ’542/’543 devices, and

Table 11 shows those associated with the ’548/’549 devices.

Table 7. Core Processor Memory-Mapped Registers

NAME

ADDRESS

DESCRIPTION

NAME

DEC

HEX

DESCRIPTION

IMR

Interrupt mask register

IFR

Interrupt flag register

–

2–5

Reserved for testing

ST0

Status register 0

ST1

Status register 1

Accumulator A low word (15–0)

Accumulator A high word (31–16)

Accumulator A guard bits (39–32)

Accumulator B low word (15–0)

Accumulator B high word (31–16)

Accumulator B guard bits (39–32)

TREG

Temporary register

TRN

Transition register

AR0

Auxiliary register 0

AR1

Auxiliary register 1

AR2

Auxiliary register 2

AR3

Auxiliary register 3

AR4

Auxiliary register 4

AR5

Auxiliary register 5

AR6

Auxiliary register 6

AR7

Auxiliary register 7

Stack pointer register

Circular buffer size register

BRC

Block-repeat counter

RSA

Block-repeat start address

REA

Block-repeat end address

PMST

Processor mode status (PMST) register

XPC

Extended program counter (’548 and ’549 only)

–

Reserved

TMS320VC549 数据表(PDF) 39 Page - Texas Instruments

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