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TMS320VC549 数据表(PDF) 86 Page - Texas Instruments |
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TMS320VC549 数据表(HTML) 86 Page - Texas Instruments |
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86 / 111 page  TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 86 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 reset, BIO, interrupt, and MP/MC timings timing requirements for reset, interrupt, BIO, and MP/MC [H = 0.5 tc(CO)] (see Figure 26, Figure 27, and Figure 28) ’C54x-40 ’LC54x-40 ’LC54x-50 ’54x-66 UNIT MIN MAX MIN MAX MIN MAX UNIT th(RS) Hold time, RS after CLKOUT low 0 0 0 ns th(BIO) Hold time, BIO after CLKOUT low 0 0 0 ns th(INT) Hold time, INTn, NMI, after CLKOUT low† 0 0 0 ns th(MPMC) Hold time, MP/MC after CLKOUT low 0 0 0 ns tw(RSL) Pulse duration, RS low‡§¶ 4H + 10 4H + 10 4H+10 ns tw(BIO)S Pulse duration, BIO low, synchronous 2H+15 2H+12 2H+10 ns tw(BIO)A Pulse duration, BIO low, asynchronous 4H 4H 4H ns tw(INTH)S Pulse duration, INTn, NMI high (synchronous) 2H+15 2H+12 2H+10 ns tw(INTH)A Pulse duration, INTn, NMI high (asynchronous) 4H 4H 4H ns tw(INTL)S Pulse duration, INTn, NMI low (synchronous) 2H+15 2H+12 2H+10 ns tw(INTL)A Pulse duration, INTn, NMI low (asynchronous) 4H 4H 4H ns tw(INTL)WKP Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup 10 10 10 ns tsu(RS) Setup time, RS before X2/CLKIN low§ 5 5 5 ns tsu(BIO) Setup time, BIO before CLKOUT low 15 12 10 ns tsu(INT) Setup time, INTn, NMI, RS before CLKOUT low 15 12 10 ns tsu(MPMC) Setup time, MP/MC before CLKOUT low 10 10 10 ns † The external interrupts (INT0 – INT3, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is corresponding to three CLKOUTs sampling sequence. ‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to assure synchronization and lock-in of the PLL. § Divide-by-two mode ¶ Note that RS may cause a change in clock frequency, therefore changing the value of H (see the PLL section). |
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