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TMS320VC5421 数据表(PDF) 22 Page - Texas Instruments

部件名 TMS320VC5421
功能描述  DIGITAL SIGNAL PROCESSOR
PDF  88 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMS320VC5421 数据表(HTML) 22 Page - Texas Instruments

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TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
software-programmable wait-state generators (continued)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SWSM
R/W=0
R/W=0
LEGEND: R = Read, W = Write
Figure 4. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 5. Software Wait-State Control Register (SWCR) Bit Fields
PIN
RESET
FUNCTION
NO.
NAME
RESET
VALUE
FUNCTION
15–1
Reserved
0
These bits are reserved and are unaffected by writes.
0
SWSM
0
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
- SWSM = 0: wait-state base values are unchanged (multiplied by 1).
- SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.
programmable bank-switching
Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank
boundaries inside program memory or data memory space. One cycle can also be inserted when crossing from
program-memory space to data-memory space (’54x) or one program memory page to another program
memory page. This extra cycle allows memory devices to release the bus before other devices start driving the
bus, thereby avoiding bus contention. The size of the memory bank for the bank-switching is defined by the
bank-switching control register (BSCR), as shown in Figure 5. The BSCR of a particular DSP subsystem
(A or B) is used for the external memory interface based on the xDMA/XIO arbitration logic.
15
14
13
12
11
10
9
8
7654
32
1
0
BNKCMP
PS-DS
Reserved
IPIRQ
Reserved
BH
Reserved
EXIO
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R = Read, W = Write
Figure 5. BSCR Register Bit Layout for Each DSP Subsystem



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