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TLC5952DAP 数据表(PDF) 19 Page - Texas Instruments |
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TLC5952DAP 数据表(HTML) 19 Page - Texas Instruments |
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19 / 33 page ![]() REGISTER AND DATA LATCH CONFIGURATION CommonShiftRegister(25Bits) LSB 0 1 Common Data Bit22 Common Data Bit23 22 23 21 20 Common Data Bit19 2 3 4 19 MSB 24 Latch Select Bit ¼ Common Data Bit21 Common Data Bit20 Common Data Bit3 Common Data Bit1 Common Data Bit4 Common Data Bit2 Common Data Bit0 SOUT SCK SIN 5 Common Data Bit5 Thelatchpulsecomes fromLATwhenthe MSBofthecommon shiftregisteris ‘0’. 24 ToOutputOn/OffControlCircuit 24 24 OutputOn/OffDataLatch(24Bits) LSB 0 1 OUTR7 On OUTG7 On 21 22 20 19 2 3 4 MSB 23 OUTB7 On ¼ OUTB6 On OUTG6 On OUTR1 On OUTG0 On OUTG1 On OUTB0 On OUTR0 On 5 OUTB1 On 24 ControlDataLatch(24Bits) 7 ToGlobalBrightness ControlCircuit forOUTB0-OUTB7 7 ToGlobalBrightness ControlCircuit forOUTR0-OUTR7 3 ToLSD/LOD Circuit ToGlobalBrightness ControlCircuit forOUTG0-OUTG7 7 Thelatchpulsecomes fromLATwhenthe MSBofthecommon shiftregisteris ‘1’. Detection Voltage Select0 Detection Voltage Select1 Detection Voltage Select2 OUTB0-7 Bright Bit6 OUTG0-7 Bright Bit6 OUTB0-7 Bright Bit0 OUTR0-7 Bright Bit6 OUTG0-7 Bright Bit0 OUTR0-7 Bright Bit0 LSB 0 21 22 20 6 7 MSB 23 ¼ 13 ¼ ¼ 14 TLC5952 www.ti.com........................................................................................................................................................................................................ SBVS129 – MAY 2009 The TLC5952 has two writable data latches: the output on/off data latch and the control data latch. Both data latches are 24 bits in length. If the common shift register MSB is '0', the least significant 24 bits of data from the 25-bit common shift register are latched into the output on/off data latch. If the MSB is '1', the data are latched into the control data latch. Figure 33 shows the common shift register and the control data latch configuration. Figure 33. Grayscale Shift Register and Data Latch Configuration Output On/Off Data Latch The output on/off data latch is 24 bits long. This latch is used to turn each output current sink (OUTRn/Gn/Bn) on or off. When the MSB of the common shift register is set to '0', the lower 24 bits are written to the output on/off data latch on the rising edge of LAT. If the output on/off data latch bit corresponding to an output is '0', the output is turned off; if the bit is a '1', the output is turned on. When the IC is powered on, the data in the output on/off data latch are not set to any default value. Therefore, the on/off control data should be written to the data latch before the constant-current outputs are turned on. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link(s): TLC5952 |
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