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TUSB3200 数据表(PDF) 38 Page - Texas Instruments |
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TUSB3200 数据表(HTML) 38 Page - Texas Instruments |
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38 / 93 page ![]() 2–22 2.2.13.4 General-Purpose Mode of Operation In the general-purpose mode the CODEC port interface can be configured to various user defined serial interface formats using the pin assignments shown in Table 2–8. This mode gives the user the flexibility to configure the TUSB3200 to connect to various CODECs and DSPs that do not use a standard serial interface format. Table 2–8. Terminal Assignments for CODEC Port Interface General-Purpose Mode TERMINAL GP NO. NAME MODE 0 35 CSYNC CSYNC I/O 34 CSCLK CSCLK I/O 36 CDATO CDAT0 O 38 CDATI CDAT1 I 39 CRESET CRESET O 40 CSCHNE NC O 2.2.14 I2C Interface The TUSB3200 has a bidirectional two-wire serial interface that can be used to access other ICs. This serial interface is compatible with the I2C (Inter IC) bus protocol and supports both 100-kbps and 400-kbps data transfer rates. The TUSB3200 is a master only device that does not support a multimaster bus environment (no bus arbitration) or wait state insertion. Hence this interface can be used to access I2C slave devices including EEPROMs and CODECs. For example, if the application program code is stored in an EEPROM on the PCB, then the MCU will download the code from the EEPROM to the TUSB3200 on-chip RAM using the I2C interface. Another example is the control of a CODEC device that uses an I2S interface for audio data transfers and an I2C interface for control register read/write access. 2.2.14.1 Data Transfers The two-wire serial interface uses the serial clock signal, SCL, and the serial data signal, SDA. As stated above, the TUSB3200 is a master only device, and therefore, the SCL signal is an output only. The SDA signal is a bidirectional signal that uses an open-drain output to allow the TUSB3200 to be wire-ORed with other devices that use open-drain or open-collector outputs. All read and write data transfers on the serial bus are initiated by a master device. The master device is also responsible for generating the clock signal used for all data transfers. The data is transferred on the bus serially one bit at a time. However, the protocol requires that the address and data be transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The timing relationship between the SCL and SDA signals for each bit transferred on the bus is shown in Figure 3-7. As shown, the SDA signal must be stable while the SCL signal is high, which also means that the SDA signal can only change states while the SCL signal is low. The timing relationship between the SCL and SDA signals for the start and stop conditions is shown in Figure 3-8. As shown, the start condition is defined as a high-to-low transition of the SDA signal while the SCL signal is high. Also as shown, the stop condition is defined as a low-to-high transition of the SDA signal while the SCL signal is high. When the TUSB3200 is the device receiving data information, the TUSB3200 will acknowledge each byte received by driving the SDA signal low during the acknowledge SCL period. During the acknowledge SCL period, the slave device must stop driving the SDA signal. If the TUSB3200 is unable to receive a byte, the SDA signal will not be driven low and should be pulled high external to the TUSB3200 device. A high during the SCL period indicates a not-acknowledge to the slave device. The acknowledge timing is shown in Figure 3-9. Read and write data transfers by the TUSB3200 device can be done using single byte or multiple byte data transfers. Therefore, the actual transfer type used depends on the protocol required by the I2C slave device being accessed. |
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