TVP3703

VIDEO INTERFACE PALETTE

TRUE-COLOR CMOS RAMDAC

SLAS100 – MARCH 1996

13

POST OFFICE BOX 655303

primary and secondary pixel mode combinations (continued)

Table 7. Primary and Secondary Pixel Mode Combinations

PRIMARY

SECONDARY MODE

PRIMARY

MODE

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

00h

X

X

X

X

01h

X

X

X

X

02h

X

X

X

X

03h

X

X

X

X

04h

X

X

X

X

05h

X

06h

X

X

X

X

07h

X

X

X

X

08h

X

X

X

X

09h

X

NOTE 2: Pixel switching can only be performed when the PCLK to dot clock ratios for the

primary and secondary modes are the same.

programming of pixel modes using the PLL

The TVP3703 uses an internal PLL to generate the internal dot clock. This PLL automatically adjusts the PCLK

to dot clock ratio based on the multiplexing mode selected. Therefore no further programming is necessary.

pixel resolution and blanking periods in mode 09h

In mode 09h (packed 24-bit), latching 16 bits of data from 3 PCLK cycles generates a group of 2 pixels. This

means that the horizontal screen resolution must be an even number of pixels, and the number of PCLK cycles

during active display must be a multiple of 3.

Due to the internal phase relationships between PCLK and the pixel clock generated by the internal PLL, the

horizontal and vertical blanking period must also be an integral multiple of 3 PCLK cycles. This must be satisfied

so that the first pixel of each line always appears at the same point horizontally on the screen, from line to line

and from frame to frame.

Therefore mode 09h requires the following relationships must be satisfied:

Horizontally:

The total horizontal duration must be an integral multiple of 3 PCLKs.

i.e.,

HTOT

3

+ integer, where HTOT + total horizontal duration in standard VGA registers.

Vertically:

The total vertical duration must be an integral multiple of 3 PCLKs.

i.e.,

VTOT

HTOT

3

+ integer, where VTOT + total vertical duration in standard VGA registers.

In all standard VGA systems, if the horizontal requirement is met, the vertical requirement is also met.

VGA standard controllers normally satisfy the requirements described in this section because the horizontal

blanking period is specified in character widths (8 pixels wide), vertical blanking in terms of scan lines, and

resolution in even pixels.