TVP3703

VIDEO INTERFACE PALETTE

TRUE-COLOR CMOS RAMDAC

SLAS100 – MARCH 1996

3

POST OFFICE BOX 655303

Terminal Functions

micro port

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

RD,

5,

I

Read enable and write enable. RD or WR control the timing of read and write operations on the micro port.

WR

20

Most of the operations on the micro port can take place asynchronously to the pixel stream being processed

by the color palette. Various minimum periods between operations are specified (in terms of pixel clocks) to

allow this asynchronous behavior.

RD and WR should not be low at the same time.

RS0 – RS2

21, 22,

50

I

Register select. RS0 – RS2 specify which internal register is to be accessed. The RS0 – RS2 inputs are sampled

on the falling edge of the active enable signal (RD or WR). Information on register access and contents is given

in the micro port section.

The additional RS2 signal allows access to the extended features without the need for performing an indirect

access sequence.

D0 – D7

12 – 19

I/O

Input/output data. Data transfers between the 8-bit wide program data bus and the registers within the TVP3703

under control of the active enable signal (RD or WR).

In a write cycle, the rising edge of WR validates the data on the program data bus and causes it to be written

to the register selected.

The rising edge of RD signifies the end of a read cycle, after which the program data bus ceases to carry the

contents of the register addressed and goes to a high impedance state.

VS0 – VS3

44 – 47

I

Video clock PLL select.VS0 – VS3 select the frequency (default or user programmed) of the video clock PLL.

VS0 – VS3 are ignored if the video clock frequency is selected by register control.

STROBE

43

I

Strobe input.The falling edge of STROBE latches VS0 – VS3.

pixel port

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

PCLK

63

I

Pixel clock. The rising edge of PCLK controls the sampling of data on P0 – P15, BLANK, and PIXMIX in all

modes.

P0 – P15

1, 4, 23,

25,

52 – 59,

64 – 67

I

Pixel data word. The selected pixel mode determines how this pixel data is interpreted.

PIXMIX

24

I

Pixel mode select. PIXMIX controls the switching between primary and secondary pixel modes when the

extended pixel modes are selected (PIXMIX = 0 selects primary mode).

BLANK

11

I

Blank in. A low value sampled on BLANK, after the pipeline delay, turns the DAC outputs off.