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PCF8576CU/2 数据表(PDF) 37 Page - NXP Semiconductors |
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PCF8576CU/2 数据表(HTML) 37 Page - NXP Semiconductors |
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37 / 56 page ![]() PCF8576C_9 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 09 — 9 July 2009 37 of 56 NXP Semiconductors PCF8576C Universal LCD driver for low multiplex rates Excessive capacitive coupling between SCL or CLK and SYNC will cause erroneous synchronization. If this is a problem you can increase the capacitance of the SYNC line (e.g. by an external capacitor between SYNC and VDD.) Degradation of the positive edge of the SYNC pulse can be countered by an external pull-up resistor. Fig 30. Synchronization of the cascade for the various PCF8576C drive modes Tfr = f fr 1 BP0 SYNC BP0 (1/2 bias) SYNC BP0 (1/3 bias) (a) static drive mode. (b) 1:2 multiplex drive mode. (c) 1:3 multiplex drive mode. (d) 1:4 multiplex drive mode. BP0 (1/3 bias) SYNC SYNC BP0 (1/3 bias) mgl755 |
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