STBP120

Pin descriptions

Doc ID 15492 Rev 4

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2

Pin descriptions

2.1

Input (IN)

Input voltage pin. This pin is connected to the DC power supply. External low ESR ceramic

capacitor of minimum value 1 µF must be connected between IN and GND. This capacitor is

for decoupling and also protects the IC against dangerous voltage spikes and ESD events.

This capacitor should be located as close to the IN pins as possible.

All IN pins (4, 5) must be hardwired to common supply.

2.2

Power output (OUT)

MOSFET switch.

If no fault is detected and the STBP120 is not disabled (controlled by the EN input), this

switch is turned on and the output voltage follows the input voltage.

The output is disconnected from the input when the input voltage is under the UVLO

threshold or above the OVLO threshold, when the chip temperature is above the thermal

shutdown threshold or when the chip is disabled by the EN input.

specified range and the power output is connected to the input (see Figure 6).

All OUT pins (6, 7) must be hardwired to common supply.

2.3

Fault indication output (FLT)

The fault indication output (active-low - open-drain) provides information on the STBP120

state to the application controller. When FLT is active (i.e. driven low), this indicates the

STBP120 is in the undervoltage or overvoltage condition or thermal shutdown mode is

active. When the input voltage and junction temperature is in specified range, the FLT output

is in high impedance (Hi-Z) state.

and the FLT output is deactivated (i.e. in Hi-Z state) (see Figure 6).

the controller supply voltage. If there is no need to use this output, it may be left

To improve safety and to prevent damage to application circuits in the event of extreme

to 100 k

Ω.

The function of the FLT output is not affected by the EN input state (see Figure 9).