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LTM9002

9002f

APPLICATIONS INFORMATION

exceed ±50mV. The internal 1000pF capacitor provides a

corner frequency of 64kHz when used with the 2.5k ex-

ternal resistor. An additional 0.1μF bypass capacitor may

be required at the SENSE pin.

The auxiliary DACs can be used without an external ref-

erence in applications that are not sensitive to close-in

phase noise such as CCD imaging or oversampling of low

amplitude signals. Without an external reference, the DAC

step size will be 366μV at the SENSE pin which results in

a 18μV step for the input span. In this case, the SENSE

pin may be bypassed with 0.1μF capacitor.

The auxiliary DACs must be subsequently set each time

the LTM9002 is powered up.

Driving the Clock Inputs

The CLK inputs can be driven directly with a CMOS or TTL

level signal. A sinusoidal clock can also be used along with a

low-jitter squaring circuit before the CLK pin (Figure 9).

The noise performance of the ADC can depend on the clock

signal quality as much as on the analog input. Any noise

present on the CLK signal will result in additional aperture

jitter that will be RMS summed with the inherent ADC

aperture jitter. In applications where jitter is critical, such

as when digitizing high input frequencies, use as large an

amplitude as possible. Also, if the ADC is clocked with a

sinusoidal signal, ﬁlter the CLK signal to reduce wideband

noise and distortion products generated by the source.

Figure 8. Using an External Reference

REF

BUFFER

10k

1.25V

1V (OPEN CIRCUIT,

4k THEVENIN

RESISTANCE)

10k

1000pF

2.5k

SENSE

RANGE

SELECT

REF

1.5V

REFERENCE

LTM9002

9002 F08

DAC

SDI

CS/LD

SCK

Figure 9. Sinusoidal Single-Ended CLK Driver

CLK

50Ω

0.1μF

4.7μF

FERRITE

BEAD

CLEAN

SUPPLY

SINUSOIDAL

CLOCK

INPUT

9002 F09

NC7SVU04

LTM9002

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