SPT7721 datasheet(11/11 Pages) CADEKA

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11/8/01

SPT7721

PIN ASSIGNMENTS

AGND

CLK

RESET

DGND

OVDD

DA6

DA7 (MSB)

DA5

DB4

DB5

DB7 (MSB)

DB6

DGND

AGND

OVDD

DMODE2

SPT7721

TOP VIEW

44L TQFP

DCLKOUT

DMODE1

CLK

RESET

DCLKOUT

DB0–DB7

Data output; Bank B. 3 V / 5 V LVCMOS

compatible.

DCLKOUT

Non-Inverted data output clock. 3 V / 5 V

LVCMOS compatible.

DCLKOUT

Inverted data output clock. 3 V / 5 V LVCMOS

compatible.

CLK

Non-Inverted clock input pin; 100k pulldown to

AGND, internally

CLK

Inverted clock input pin; 17.5k pullup to VCC and

7.5k pulldown to AGND, internally

RESET

RESET synchronizes the data sampling and data

output bank relationship when in Dual Channel

Mode (DMODE1 = 0); 100k pulldown to AGND,

internally

RESET

Inverted RESET input pin; 17.5k pullup to VCC

and 7.5k pulldown to AGND, internally

DMODE1,2

Internally:

100k pulldown to AGND on DMODE1

50k pullup to VCC on DMODE2

Data Output Mode pins:

DMODE1 = 0, DMODE2 = 0: Parallel Dual

Channel Output

DMODE1 = 0, DMODE2 = 1: Interleaved Dual

Channel Output

DMODE1 = 1, DMODE2 = X: Single Channel

Data Output on Bank A (125 MSPS max)

Power Down pin; PD = 1 for power-down mode.

Outputs set to high impedance in power-down

mode; 100k pulldown to AGND, internally

VCM

2.5 V Common Mode Voltage Reference Output

AVCC

+5 V Analog Supply

OVDD

+3 V / +5 V Digital Output Supply

AGND

Analog Ground

DGND

Digital Ground

ORDERING INFORMATION

PART NUMBER

TEMPERATURE RANGE

PACKAGE

SPT7721SIT

–40 to +85 °C

44L TQFP

PIN FUNCTIONS

Pin Name

Description

VIN+

Non-Inverted Analog Input; nominally 1 VP-P;

100k pullup to VCC and 100k pulldown to AGND,

internally

VIN–

Inverted Analog Input; nominally 1 VP-P; 100k

pullup to VCC and 100k pulldown to AGND,

internally

DA0–DA7

Data output; Bank A. 3 V / 5 V LVCMOS

compatible.

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