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SPT7871 数据表(PDF) 2 Page - Cadeka Microcircuits LLC. |
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SPT7871 数据表(HTML) 2 Page - Cadeka Microcircuits LLC. |
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2 / 8 page  2 9/7/98 SPT7871 ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)1 Supply Voltages AVCC ........................................................................ 0 to +6.5 V DVCC ........................................................................ 0 to +6.5 V VEE ............................................................................. 0 to -6.5 V Input Voltages Analog Input ............................................. VEE≤VIN≤VCC LINV/MINV Inputs .......................... -0.5 V to VCC +0.5 V CLK/NCLK Inputs ........................................... VEE to 0 V Output Digital Outputs ......................................... +30 to -30 mA Temperature Operating Temperature ............................. -40 to + 85 °C Junction Temperature ........................................ + 175 °C Lead, Soldering (10 seconds) ............................ + 300 °C Storage .................................................... -60 to + 150 °C Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. DC Performance Resolution 10 Bits Differential Linearity fClock = 6.4 MHz I -1.0 ±0.5 ±1.25 LSB Integral Linearity, Best Fit fClock = 6.4 MHz I ±1.0 ±2.0 LSB Full Temperature V ±2.5 LSB No Missing Codes fClock = 6.4 MHz I Guaranteed Analog Input Input Voltage Range V ±1.0 V Input Bias Current I -100 25 100 µA Input Resistance I 50 150 k Ω Full Temperature V 100 k Ω Input Capacitance V 5 pF Input Bandwidth Full Power IV 150 180 MHz ±FS Offset Error I ±20 ±100 mV Timing Characteristics Minimum Conversion Rate V 2 MSPS Maximum Conversion Rate IV 100 MSPS Pipeline Delay (Latency) IV 2 Clock Transient Response V 10 ns Overvoltage Recovery Time V 10 ns Output Delay (td)V 3 ns Aperture Delay Time V 1 ns Aperture Jitter Time V 5 ps (rms) Dynamic Performance Effective Number of Bits fIN = 10 MHz I 8.1 8.5 Bits fIN = 25 MHz I 8.1 8.5 Bits fIN = 25 MHz fclock = 100 MHz V 8.0 Bits fIN = 50 MHz I 7.5 7.8 Bits fIN = 50 MHz fclock = 100 MHz V 7.5 Bits Signal-To-Noise Ratio fIN = 10 MHz I 52 54 dB fIN = 25 MHz I 52 54 dB fIN = 25 MHz fclock = 100 MHz V 51 dB fIN = 50 MHz I 52 54 dB fIN = 50 MHz fclock = 100 MHz V 50 dB Total Harmonic Distortion1 fIN = 10 MHz I -56 -62 dBc fIN = 25 MHz I -56 -60 dBc fIN = 25 MHz fclock = 100 MHz V -56 dBc fIN = 50 MHz I -48 -51 dBc fIN = 50 MHz fclock = 100 MHz V -50 dBc TA = +25 °C , DVCC =AVCC = +5.0 V, VEE = -5.2 V, VIN = ±1.0 V, fclock = 80 MHz, 50% clock duty cycle, unless otherwise specified. TEST TEST PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS ELECTRICAL SPECIFICATIONS |
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