TMC3003 datasheet(9/12 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC3003

REV. 1.0.3 3/5/01

Applications Discussion

Figure 4 illustrates a typical TMC3003 interface circuit.

In this example, an optional 1.2 Volt bandgap reference is

connected to the VREF output, overriding the internal volt-

age reference source.

Grounding

It is important that the TMC3003 power supply is well-

regulated and free of high-frequency noise. Careful power

supply decoupling will ensure the highest quality video sig-

nals at the output of the circuit. The TMC3003 has separate

analog and digital circuits. To keep digital system noise from

the D/A converter, it is recommended that power

supply voltages (VDD) come from the system analog power

source and all ground connections (GND) be made to the

analog ground plane. Power supply pins should be individu-

ally decoupled at the pin.

Printed Circuit Board Layout

Designing with high-performance mixed-signal circuits

demands printed circuits with ground planes. Overall

system performance is strongly inﬂuenced by the board lay-

out. Capacitive coupling from digital to analog circuits may

result in poor D/A conversion. Consider the following

suggestions when doing the layout:

Keep the critical analog traces (VREF, IREF, COMP,

IOR, IOG, IOB) as short as possible and as far as possi-

ble from all digital signals. The TMC3003 should be

located near the board edge, close to the analog output

connectors.

The power plane for the TMC3003 should be separate

from that which supplies the digital circuitry. A single

power plane should be used for all of the VDD pins. If

the power supply for the TMC3003 is the same as that of

the system's digital circuitry, power to the TMC3003

should be decoupled with 0.1µF and 0.01µF capacitors

and isolated with a ferrite bead.

The ground plane should be solid, not cross-hatched.

Connections to the ground plane should have very short

leads.

If the digital power supply has a dedicated power plane

layer, it should not be placed under the TMC3003, the

voltage reference, or the analog outputs. Capacitive cou-

pling of digital power supply noise from this layer to the

TMC3003 and its related analog circuitry can have an

adverse effect on performance.

CLK should be handled carefully. Jitter and noise on

this clock will degrade performance. Terminate the

clock line carefully to eliminate overshoot and ringing.

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