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QPI-9 Data Sheet Rev. 1.3 Page 2 of 8

Pins

Parameter

Notes

Min

Typ

Max

Units

BUS+, SW, PWRGD1,

Input voltage

Continuous

-0.5

40

Vdc

PWRGD2 to BUS-

BUS+, SW, PWRGD1,

Input voltage

100 mSec Transient

100

Vdc

PWRGD2 to BUS-

BUS+/BUS- to shield

BUS Inputs to shield hipot

+/-707

Vdc

QPI+ to QPI-

Input to output current

Pulsed Limit @ 25°C

12

Adc

Package

Power Dissipation

VBUS = 24 V, 6 Adc, 25°C

3.0

W

Package

Operating Temperature

PCB to QPI Interface

-40

100

°C

Package

Thermal Resistance

Free Air

50

°C/W

Package

Junction Temperature

Tb = 100 °C Pd = 3 W @15 °C/W

145

°C

Package

Thermal Resistance

PCB Layout Dependent

(1)

15

°C/W

Package

Storage Temperature

-40

125

°C

Package

Re-flow Temperature

20 s exposure @

(2)

212

°C

All Pins

ESD

HBM

+/-2

kV

Note 1: Refer to Figure 15 and 16 for critical PCB layout guidelines to achieve this thermal resistance when reflowed onto the PCB.

Note 2: RoHS compliant product maximum peak temperature is 245°C for 20 seconds.

QPI-9

SiP Package

(Bottom View)

9

10

11

12

4

3

2

1

8

7

6

5

13

14

15

16

PWRGD2

PWRGD1

OV

BUS+

SHIELD

SW

BUS-

QPI+

QPI-

BUS+

UVEN

SW

BUS-

Pad Description

Pin

Number

Name

Description

1, 16

BUS-

Negative bus potential

2, 3, 15

SW

Negative rail controlled by hot insertion

function.

4

SHIELD

Shield connects to the filter's shield pad

and the chassis's common pin

5, 6

QPI-

Negative input to the converter

7, 8

QPI+

Positive input to the converter

10

PWRGD1

Open drain, referenced to BUS-, that

asserts low when power is NOT good

9

PWRGD2

Open drain, referenced to QPI-, that

asserts low when power is NOT good

12, 13

BUS+

Positive bus potential

14

UVEN

Highside of UV resistor divider

11

OV

Highside of OV resistor divider

Symbol

Parameter

Notes

Min

Typ

Max

Units

Vb+b-

BUS+ to BUS- input range

Measured at 5 A

(3)

UV

38

Vdc

V+oi

BUS+ to QPI+ voltage drop

Measured at 5 A

(3)

110

mVdc

V-oi

BUS- to QPI- voltage drop

Measured at 5 A

(3)

-380

mVdc

CMIL

Common-mode insertion loss

VBUS = 48 V frequency =1 MHz

50

dB

DMIL

Differential-mode insertion loss

VBUS = 48 V frequency =1 MHz

70

dB

I BUS + to BUS-

Input bias current at 80 V

Input current from BUS+ to BUS-

10

mA

IPG QPI+ to QPI- Load current prior to PWRGD

Critical maximum DC load

25

mA

UV

Undervoltage threshold - rising

Controller disabled to enabled

18

V

UVHYS

Undervoltage hysteresis - falling

Controller enabled to disabled

UV - 2 V

V

OV

Overvoltage threshold - rising

Controller enabled to disabled

38

V

OVHYS

Overvoltage hysteresis - falling

Controller disabled to enabled

OV - 2 V

V

PWRGD1SAT

Power Good low voltage

IPWG = 1 mA, referenced to BUS-

0.2

0.6

mV

PWRGD2SAT

Power Good low voltage

IPWG = 1 mA, referenced to QPI-

0.2

0.6

mV

PWGLK

Power Good high leakage

VPWG = 40 V

1

µA

Note 3: Refer to Figure 5 for current derating curve.