CS2100-CP_09 datasheet(19/32 Pages) CIRRUS

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CS2100-CP

DS840F1

5.3.3

Effective Ratio (REFF)

The Effective Ratio (REFF) is an internal calculation comprised of RUD and the appropriate modifiers, as

previously described. REFF is calculated as follows:

REFF = RUD

• R

MOD

To simplify operation the device handles some of the ratio calculation functions automatically (such as

when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need

to be altered to account for internal dividers.

Ratio modifiers which would produce an overflow or truncation of REFF should not be used; For example

if RUD is 1024 an RMOD of 8 would produce an REFF value of 8192 which exceeds the 4096 limit of the

12.20 format. In all cases, the maximum and minimum allowable values for REFF are dictated by the fre-

quency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on

page 7.

5.3.4

Ratio Configuration Summary

The RUD is the user defined ratio stored in the register space. The resolution for the RUD is selectable by

setting LFRatioCfg. R-Mod is applied if selected. The user defined ratio, and ratio modifier make up the

effective ratio REFF, the final calculation used to determine the output to input clock ratio. The effective

ratio is then corrected for the internal dividers. The conceptual diagram in Figure 17 summarizes the fea-

tures involved in the calculation of the ratio values used to generate the fractional-N value which controls

the Frequency Synthesizer.

Figure 17. Ratio Feature Summary

Referenced Control

Ratio...................................... “Ratio (Address 06h - 09h)” on page 27

LFRatioCfg ............................ “Low-Frequency Ratio Configuration (LFRatioCfg)” on page 29

RModSel[2:0] ........................ “R-Mod Selection (RModSel[2:0])” section on page 26

RefClkDiv[1:0] ....................... “Reference Clock Input Divider (RefClkDiv[1:0])” on page 28

Effective Ratio REFF

Ratio Format

Frequency Reference Clock

(CLK_IN)

SysClk

PLL Output

Frequency

Synthesizer

Digital PLL &

Fractional N Logic

Ratio

12.20

20.12

LFRatioCfg

RModSel[2:0]

Ratio

Modifier

R Correction

RefClkDiv[1:0]

Timing Reference Clock

(XTI/REF_CLK)

Divide

RefClkDiv[1:0]

User Defined Ratio RUD

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