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CS8421 数据表(PDF) 13 Page - Cirrus Logic

部件名 CS8421
功能描述  32-bit, 192 kHz Asynchronous Sample Rate Converter
PDF  38 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS8421 数据表(HTML) 13 Page - Cirrus Logic

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DS641F2
13
CS8421
DIGITAL INPUT CHARACTERISTICS
DIGITAL INTERFACE SPECIFICATIONS
(GND = 0 V; all voltages with respect to 0 V.)
SWITCHING SPECIFICATIONS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameters
Symbol
Min
Typ
Max
Units
Input Leakage Current
Iin
--
±10
μA
Input Capacitance
Iin
-8
-
pF
Input Hysteresis
-250
-
mV
Parameters
Symbol
Min
Max
Units
High-Level Output Voltage, except MCLK_OUT and SDOUT (IOH=-4 mA)
VOH
0.77xVL
-
V
Low-Level Output Voltage, except MCLK_OUT and SDOUT (IOL=4 mA)
VOL
-.6
V
High-Level Output Voltage, MCLK_OUT
(IOH=-6 mA)
VOH
0.77xVL
-
V
Low-Level Output Voltage, MCLK_OUT
(IOL=6 mA)
VOL
-.6
V
High-Level Output Voltage, SDOUT
(IOH=-8 mA)
VOH
0.77xVL
-
V
Low-Level Output Voltage, SDOUT
(IOL=8 mA)
VOL
-.65
V
High-Level Input Voltage
VIH
0.6xVL
VL+0.3
V
Low-Level Input Voltage
VIL
-0.3
0.8
V
Parameters
Symbol
Min
Max
Units
RST pin Low Pulse Width
(Note 6)
1-
ms
XTI Frequency (Note 7)
Crystal
Digital Clock Source
16.384
1.024
27.000
27.000
MHz
MHz
XTI Pulse Width High/Low
14.8
-
ns
MCLK_OUT Duty Cycle
45
55
%
Slave Mode
I/OSCLK Frequency
-
24.576
MHz
OLRCK High Time
(Note 8)
tlrckh
326
-
ns
I/OSCLK High Time
tsckh
9-
ns
I/OSCLK Low Time
tsckl
9-
ns
I/OLRCK Edge to I/OSCLK Rising
tlcks
6-
ns
OLRCK Rising Edge to OSCLK Rising Edge (TDM)
tfss
5-
ns
I/OSCLK Rising Edge to I/OLRCK Edge
tlckd
5-
ns
OSCLK Rising Edge to OLRCK Falling Edge (TDM)
tfsh
5-
ns
OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid
tdpd
-18
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
tds
3.5
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
tdh
5-
ns



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