DS641F2

17

CS8421

4. APPLICATIONS

The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter.

The digital audio data is input and output through configurable 3-wire serial ports. The digital audio input/output ports

offer Left-Justified, Right-Justified, and I²S serial audio formats. The CS8421 also supports a TDM Mode which al-

lows multiple channels of digital audio data on one serial line. A Bypass Mode allows the data to be passed directly

to the output port without sample rate conversion.

The CS8421 does not require a control port interface, helping to speed design time by not requiring the user to de-

velop software to configure the part. Pins that are sensed after reset allow the part to be configured. See “Reset,

Power-Down, and Start-Up” on page 23.

Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mix-

ing consoles, high quality D/A, effects processors and computer audio systems.

Figure 5 and 6 show the supply and external connections to the CS8421.

4.1

Three-wire Serial input/Output Audio Port

A 3-wire serial audio input/output port is provided. The interface format should be chosen to suit the attached device

through the MS_SEL, SAIF, and SAOF pins. Tables 1, 2, and 3 show the pin functions and their corresponding set-

tings. The following parameters are adjustable:

•

Master or Slave

•

Master clock (MCLK) frequencies of 128*Fsi/o, 256*Fsi/o, 384*Fsi/o, and 512*Fsi/o (Master Mode)

•

Audio data resolution of 16-, 20-, 24-, or 32-bits

•

Left- or Right-Justification of the data relative to left/right clock (LRCK) as well as I²S

Figures 7, 8, and 9 show the input/output formats available.

In Master Mode, the left/right clock and the serial bit clock are outputs, derived from the XTI input pin master clock.

In Slave Mode, the left/right clock and the serial bit clock are inputs and may be asynchronous to the XTI master

clock. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough serial clocks are

present in each phase to clock all of the data bits.

ISCLK is always set to 64*Fsi when the input is set to master. In normal operation, OSCLK is set to 64*Fso. In TDM

Slave Mode, OSCLK must operate at N*64*Fso, where N is the number of CS8421’s connected together. In TDM

Master Mode, OSCLK is set to 256*Fso

For more information about serial audio formats, refer to the Cirrus Logic applications note AN282, “The 2-Channel

Serial Audio Interface: A Tutorial”, available at www.cirrus.com.