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ATS682LSH 数据表(PDF) 12 Page - Allegro MicroSystems |
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ATS682LSH 数据表(HTML) 12 Page - Allegro MicroSystems |
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12 / 16 page ![]() Miniature, Two-Wire, True Zero Speed Differential Peak-Detecting Sensor IC ATS682LSH 12 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Device Operation Power-On When power (VCC > VCC(min)) is applied to the device, a short period of time is required to activate the various portions of the IC. During this period, the ATS682 powers-on in the high current state, ICC(HIGH). After power-on, there are condi- tions that could induce a change in the output state. Such an event could be caused by thermal transients, but it would also require a static applied magnetic field, proper signal polarity, and particular direction and magnitude of internal signal drift. Initial Offset Adjust The IC initially compensates for differ- ential offset, ΔBAPP, that results from chip, magnet, and instal- lation alignment. Once the effective differential magnetic offset has been cancelled, the digital tracking DAC is ready to track the signal and provide output switching. The period of time required for both power-on and initial offset adjust is defined as the Power-On Time specification. Calibration Mode The calibration mode allows the IC to auto- matically select the proper signal gain and continue to adjust for DC differential magnetic offset. The AGC is active, and selects the optimal signal gain based on the amplitude of the VPROC signal. Following each adjustment to the AGC DAC, the Offset DAC is also adjusted to ensure the internal analog signal is prop- erly centered. During this mode, the tracking DAC is active and output switching occurs, but the duty cycle is not guaranteed to be within specification. Running Mode After the initial calibration process (CALI edges) establishes a signal gain, the device moves to Running mode. During Running mode, the IC tracks the input signal and continues to give an output edge for every peak of the signal. AOA remains active to compensate for any offset drift over time. The ATS682 also incorporates an algorithm for adjusting the signal gain during Running mode. This algorithm is designed to optimize the VPROC signal amplitude in instances where the mag- netic signal during the calibration period is not representative of the amplitude of the magnetic signal for the installed application air gap (see figure 9). IC Electrical Output, I OUT Internal Differential Signal, V PROC BRP BOP BOP BRP 1 2 3 4 5 Figure 9: Operation of Running Mode Gain Adjust. Position 1. The device is initially powered-on. Self-calibration occurs. Position 2. Small amplitude oscillation of the target sends an erroneously small differential signal to the device. The amplitude of VPROC is greater than the switching hysteresis (BOP and BRP), and the device output switches. Position 3. The calibration period completes on the third rising output edge, and the device enters Running mode. Position 4. True target rotation occurs and the correct magnetic signal is generated for the installation air gap. The established signal gain is too large for the rotational magnetic signal of the target, at the given air gap. Position 5. Running mode calibration corrects the signal gain to an optimal level for the installation air gap. |
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