AD8120

Rev. 0 | Page 12 of 16

of a clock input and a bidirectional data line. The AD8120

drives the SDA line either to acknowledge the master (ACK) or

port is open drain and requires a 10 kΩ pull-up resistor.

Pin No.

Pin Name

Description

2

SDA

Serial data input/output

30

SCL

Serial clock input

29

A1

31

A0

The AD8120 address consists of a built-in address of 0x38 and the

two address pins, A0 and A1. The two address pins enable up to

four AD8120 devices to be used in a system (see Table 10). Both

address pins must be terminated (high or low) for the AD8120

A1 Pin

A0 Pin

0

0

0x38

0

1

0x39

1

0

0x3A

1

1

0x3B

for a write operation (see Figure 19) and a 4-byte sequence for a

read operation (see Figure 20). The first byte contains the 7-bit

device address and the R/W instruction bit. The second byte con-

tains the color register.

In write mode, the third byte contains the delay code. In read

mode, the third byte contains the device address, and the fourth

byte contains the stored delay code.

START BY

MASTER

STOP BY

MASTER

ACK BY

AD8120

ACK BY

AD8120

ACK BY

AD8120

0

11

9

1

1

1

0

A1

A0

0

0

00

0

0

0

C1

C0

SCL

SD

9

A

SDA (CONTINUED)

SCL (CONTINUED)

9

1

X

X

D5

D4

D3

D2

D1

D0

R/W

BYTE 1

BYTE 2

COLOR REGISTER

BYTE 3

DELAY DATA CODE

START BY

MASTER

ACK BY

AD8120

ACK BY

AD8120

R/W

SCL

11

9

9

SDA

01

1

1

0

01

1

10

A1

A0

0

0

0

0

0

0

0

C1

C0

BYTE 1

BYTE 2

COLOR REGISTER

BYTE 3

BYTE 4

DATA BYTE FROM AD8120

STOP BY

MASTER

START BY

MASTER

ACK BY

AD8120

NO ACK BY

AD8120

SCL

11

9

9

SDA

A1

A0

1

X

X

D5

D4

D3

D2

D1

D0

R/W