AD8264ACPZ-R7 datasheet(28/40 Pages) AD

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AD8264

Rev. 0 | Page 28 of 40

THEORY OF OPERATION

OVERVIEW

The AD8264 is a dc-coupled quad channel VGA with a fixed

gain-of-2 (6 dB) preamplifier and a single-ended-to-differential

output amplifier with level shift capability that can be used as an

ADC driver. Figure 111 shows a representative block diagram of

a single channel; all four channels are identical. The supply can

operate from ±2.5 V to ±5 V. The primary application is as a

pulse processor for medical positron emission tomography

(PET) imaging; however, the part is useful for any dc-coupled

application that can benefit from variable gain.

The signal chain consists of three fundamental stages: the

preamplifier, the variable gain amplifier, and the differential

output buffer amplifier. The preamplifier has an internally fixed

gain-of-2 (6 dB). The VGA comprises an attenuator that

provides 0 dB to 24 dB of attenuation, followed by a fixed gain

18 dB (8×) amplifier. The single-ended VGA output is connected

directly to the noninverting input of the differential output

(post) amplifier, which has a differential fixed gain-of-2 (6 dB).

The gain range from the preamp input to the VGA output is

0 dB to 24 dB. The aggregate gain range from preamp input to

the differential postamplifier output is 6 dB to 30 dB.

The ideal gain equation for the gain from the single-ended

input to the output is

VGAIN = VGNHx − VGNLO

(1)

ICPT

Gain

GAIN +

(2)

The ideal value for ICPT, or the intercept, is defined at VGAIN = 0 V.

The ICPT for the VGA output and differential amplifier outputs

equals 12.1 dB and 18.1 dB, respectively. The actual intercept

varies with any additional gain or loss along the signal path.

The measured values are both approximately 0.2 dB low.

PREAMP

The preamplifier is a current feedback amplifier, designed to

drive the internal 100 Ω gain setting resistors and the resistive

attenuator, which together result in a nominal load to the

preamplifier of about 113 Ω. Normally, the negative preamp

input, IPNx, is not connected externally. The positive input

IPPx is the high impedance input of the current feedback amp.

Note that, at the largest supply voltage of ±5 V, the input signal

can become so large that the preamplifier output cannot deliver

the required current to drive the 113 Ω load and, therefore, limits

at 6 V p-p. This means that the input limits at 3 V p-p.

The short-circuit input referred noise at maximum VGA gain is

about 2.3 nV/√Hz, and this accounts for all of the amplifiers and

gain setting resistors. When measuring the input referred noise

from the VGA output, the number is slightly lower at 2.1 nV/√Hz

because the noise of the postamplifier is not included in the

noise calculation.

VGA

The VGA has a voltage feedback architecture and uses analog

control to vary the gain. Its low gain range helps to maintain

low offset and is intended for gain trim applications. The offset

of the preamp and the VGA are trimmed; therefore, the maximum

input referred offset is <0.5 mV over temperature (see Figure 26).

Keeping the gain of each stage relatively low also allows the

bandwidth to stay high.

The gain of the VGA is adjusted using the fully differential

control inputs, GNHx and GNLO. The GNLO pin is internally

connected to all four channels and must be biased externally.

Under typical conditions, the GNLO pin is grounded. The gain

high control pins (GNHx) are independent for each channel.

The gain slope is nominally 20 dB/V. With GNLO connected to

ground, each GNHx input can have a voltage applied from VNEG

to VPOS without gain foldover.

To make use of the full gain range of the VGA, the nominal gain

control voltage needed at GNHx is ±0.65 V relative to the voltage

applied to GNLO. At the lowest supply voltage of ±2.5 V, the pin

GNLO should always be grounded. With increasing supply, the

common-mode range of the gain control interface increases.

This means that GNLO can be anywhere within ±1.2 V at

±3.3 V supplies and ±2.8 V at ±5 V supplies.

Table 5. Gain Control Input Range

Supply Voltage (V)

GNLO Voltage Range (V)

VGAIN Range (V)

±5

±2.8

±0.65

±3.3

±1.2

±0.65

±2.5

±0.65

For example, at ±3.3 V supplies, the outputs of a single-supply

unipolar DAC, such as the 10-bit, 4-channel AD5314, can be

used to drive the GNHx pins directly, in conjunction with using

the ADR318 1.8 V reference to bias the GNLO pin at VREF/2 = 0.9.

Because the GNLO pin sources only about 1.2 μA for the four

channels (~300 nA per channel, the same as for the GNHx pins), a

simple resistive divider is generally adequate to set the voltage at

the GNLO input.

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