AD8465

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APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The AD8465 comparator is a very high speed device. Despite

the low noise output stage, it is essential to use proper high

speed design techniques to achieve the specified performance.

Because the comparator is an uncompensated amplifier, feedback

in any phase relationship is likely to cause oscillations or undesired

hysteresis. The use of low impedance supply planes is of critical

and the ground plane (GND). Individual supply planes are

recommended as part of a multilayer board. Providing the

lowest inductance return path for switching currents ensures

the best possible performance in the target application.

It is also important to adequately bypass the input and output

supplies. Place multiple high quality 0.01 μF bypass capacitors

connect the capacitors to the GND plane with redundant vias.

Place at least one capacitor to provide a physically short return

capacitors for minimum inductance and ESR. Parasitic layout

inductance should also be strictly controlled to maximize the

effectiveness of the bypass at high frequencies.

The input and output supplies have been connected separately

to the GND plane. Do not connect a bypass capacitor between

these supplies. It is recommended that the GND plane separate

to minimize coupling between the two supplies to take advan-

tage of the additional bypass capacitance from each respective

supply to the ground plane. This enhances the performance when

split input/output supplies are used. If the input and output supplies

coupling between the two supplies is unavoidable; however,

careful board placement can help keep output return currents

away from the inputs.

LVDS-COMPATIBLE OUTPUT STAGE

Specified propagation delay dispersion performance is only

achieved by keeping parasitic capacitive loads at or below the

specified minimums. The outputs of the AD8465 are designed

to directly drive any standard LVDS-compatible input.

USING/DISABLING THE LATCH FEATURE

The latch input is designed for maximum versatility. It can

safely be left floating or it can be driven low by any standard

TTL/CMOS device as a high speed latch. In addition, the pin

can be operated as a hysteresis control pin with a bias voltage

of 1.25 V nominal and an input resistance of approximately

70 kΩ. This allows the comparator hysteresis to be easily

controlled by either a resistor or an inexpensive CMOS DAC.

Driving this pin high or floating the pin disables all hysteresis.

Hysteresis control and latch mode can be used together if an

open drain, an open collector, or a three-state driver is connected

in parallel to the hysteresis control resistor or current source.

Due to the programmable hysteresis feature, the logic threshold

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout

techniques are essential for obtaining the specified performance.

Stray capacitance, inductance, inductive power and ground imped-

ances, or other layout issues can severely limit performance and

often cause oscillation. Large discontinuities along input and

output transmission lines can also limit the specified pulse width

dispersion performance. Minimize the source impedance as

much as is practicable. High source impedance, in combina-

tion with the parasitic input capacitance of the comparator,

causes an undesirable degradation in bandwidth at the input,

thus degrading the overall response. Thermal noise from large

resistances can easily cause extra jitter with slowly slewing input

signals. Higher impedances encourage undesired coupling.