ADL5331

Rev. 0 | Page 11 of 16

10nF

10nF

INHI

INLO

RFOUT

RFIN

10nF

10nF

OPHI

OPLO

ADL5331

RF VGA

120nH

120nH

5V

ETC1-1-13

Figure 17. Single-Ended Drive with Balanced Output

The device can be driven single-ended with similar perfor-

mance, as shown in Figure 17. The single-ended input interface

can be implemented by driving one of the input terminals and

terminating the unused input to ground. To achieve the optimal

performance, the output must remain balanced. In the case of

Figure 17, a transformer balun is used at the output.

GAIN CONTROL INPUT

When the VGA is enabled, the voltage applied to the GAIN pin

sets the gain. The input impedance of the GAIN pin is 1 MΩ.

The gain control voltage range is between 0.1 V and 1.4 V,

which corresponds to a typical gain range between −15 dB and

+15 dB.

The 1 dB input compression point remains constant at 3 dBm

through the majority of the gain control range, as shown in

Figure 7 through Figure 9. The output compression point

increases decibel for decibel with increasing gain setting. The

The bandwidth on the gain control pin is approximately 3 MHz.

Although the ADL5331 provides accurate gain control, precise

regulation of output power can be achieved with an automatic

gain control (AGC) loop. Figure 18 shows the ADL5331 in an

AGC loop. The addition of a log amp or a TruPwr™ detector

(such as the AD8362) allows the AGC to have improved

temperature stability over a wide output power control range.

Note that the ADL5331, because of its positive gain slope, in

Figure 19 has a negative slope. The AD8362 rms detector,

however, has a positive slope. Extra circuitry is necessary to

compensate for this.

To operate the ADL5331 in an AGC loop, a sample of the

output RF must be fed back to the detector (typically using

a directional coupler and additional attenuation). A setpoint

voltage is applied to the VSET input of the detector while VOUT

is connected to the GAIN pin of the ADL5331. Based on the

detector’s defined linear-in-dB relationship between VOUT

and the RFIN signal, the detector adjusts the voltage on the

GAIN pin (the detector’s VOUT pin is an error amplifier

output) until the level at the RF input corresponds to the applied

in the correct balance between the input signal level at the

detector and the setpoint voltage.

The detector’s error amplifier uses CLPF, a ground-referenced

capacitor pin, to integrate the error signal (in the form of a

current). A capacitor must be connected to CLPF to set the

loop bandwidth and to ensure loop stability.

INLO

INHI

GAIN

OPLO

OPHI

DIRECTIONAL

COUPLER

ATTENUATOR

VPOS

COMM

ADL5331

5V

5V

CLPF

VOUT

VSET

RFIN

LOG AMP OR

TruPwr

DETECTOR

DAC

RFIN

Figure 18. ADL5331 in AGC Loop