MCP6021 datasheet(18/42 Pages) MICROCHIP

18 / 42 page

MCP6021/1R/2/3/4

DS21685D-page 18

When driving large capacitive loads with these op

amps (e.g., > 60 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-3) improves the

feedback loop’s phase margin (stability) by making the

load resistive at higher frequencies. The bandwidth will

be generally lower than the bandwidth with no

capacitive load.

FIGURE 4-3:

Output Resistor RISO

Stabilizes Large Capacitive Loads.

Figure 4-4 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-4:

Recommended RISO values

for capacitive loads.

After selecting RISO for your circuit, double-check the

resulting

frequency

response

peaking

and

step

response overshoot. Modify RISO’s value until the

response is reasonable. Evaluation on the bench and

simulations with the MCP6021/1R/2/3/4 Spice macro

model are helpful.

4.4

Gain Peaking

Figure 2-35 and Figure 2-36 use RF =1kΩ to avoid

(frequency

response)

gain

peaking

and

(step

response) overshoot. The capacitance to ground at the

inverting input (CG) is the op amp’s common mode

input capacitance plus board parasitic capacitance. CG

is in parallel with RG, which causes an increase in gain

at high frequencies for non-inverting gains greater than

1 V/V (unity gain). CG also reduces the phase margin

of the feedback loop for both non-inverting and

inverting gains.

FIGURE 4-5:

Non-inverting Gain Circuit

with Parasitic Capacitance.

The largest value of RF in Figure 4-5 that should be

used is a function of noise gain (see GN in Section 4.3

“Capacitive Loads”) and CG. Figure 4-6 shows results

for various conditions. Other compensation techniques

may be used, but they tend to be more complicated to

the design.

FIGURE 4-6:

Non-inverting gain circuit

with parasitic capacitance.

4.5

MCP6023 Chip Select (CS)

The MCP6023 is a single amplifier with chip select

(CS). When CS is pulled high, the supply current drops

to 10 nA (typical) and flows through the CS pin to VSS.

When this happens, the amplifier output is put into a

high-impedance state. By pulling CS low, the amplifier

is enabled. The CS pin has an internal 5 M

Ω (typical)

pulldown resistor connected to VSS, so it will go low if

the CS pin is left floating. Figure 1-1 and Figure 2-39

show the output voltage and supply current response to

a CS pulse.

VIN

MCP602X

RISO

VOUT

100

1,000

100

1,000

10,000

Normalized Capacitance; CL/GN (pF)

GN ≥ +1

VIN

VOUT

1.E+02

1.E+03

1.E+04

1.E+05

110

Noise Gain; GN (V/V)

GN > +1 V/V

100

10k

100k

CG = 7 pF

CG = 20 pF

CG = 50 pF

CG = 100 pF

MCP6021 数据表(PDF) 18 Page - Microchip Technology

MCP6021 数据表(HTML) 18 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载